systemverilog-hdl Open-Source Projects

cva6

10 2,100 9.7 Assembly

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Project mention: CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux | news.ycombinator.com | 2023-11-15

vunit

10 688 8.2 VHDL

VUnit is a unit testing framework for VHDL/SystemVerilog
InfluxDB

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

systemverilog-hdl related posts

CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux

1 project | news.ycombinator.com | 15 Nov 2023
Software languages vs HDLs for verification

3 projects | /r/FPGA | 11 Feb 2023
Libero - Inefficient Simulations

1 project | /r/FPGA | 29 Jan 2023
Books About Testing and Verification

2 projects | /r/FPGA | 25 Jan 2023
A couple of questions for the experts

2 projects | /r/FPGA | 22 Dec 2022
The CORE-V CVA6 is a RISC-V CPU capable of booting Linux

1 project | news.ycombinator.com | 23 Oct 2022
SystemVerilog testbench library

1 project | /r/FPGA | 14 Sep 2022
A note from our sponsor - InfluxDB
www.influxdata.com | 21 May 2024

Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality. Learn more →