hardware-description-language

Open-source projects categorized as hardware-description-language
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Language: + Haskell + Python + Coq + Verilog + C#
Topics: Fpga Vhdl Verilog Asic coq
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Top 10 hardware-description-language Open-Source Projects

  • clash-ghc

    Haskell to VHDL/Verilog/SystemVerilog compiler

    • Project mention: Clash: A Functional Hardware Description Language | news.ycombinator.com | 2023-12-27

  • awesome-hdl

    Hardware Description Languages

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  • PipelineC

    A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

    • Project mention: PipelineC Example: FM Radio Demodulation (FPGA SDR) | news.ycombinator.com | 2024-03-03

    Related: PipelineC: A C-like hardware description language (HDL):

    https://github.com/JulianKemmerer/PipelineC

  • systemrdl-compiler

    SystemRDL 2.0 language compiler front-end

  • kami

    A Platform for High-Level Parametric Hardware Specification and its Modular Verification (by mit-plv)

    • Project mention: Kami: A Platform for Hardware Specification and Verification | news.ycombinator.com | 2023-12-28

  • koika

    A core language for rule-based hardware design 🦑

  • filament

    Fearless hardware design (by cucapra)

    • Project mention: Engineer creates CPU from scratch in two weeks – begins work on GPUs | news.ycombinator.com | 2024-04-15

    Verilog is kind of trash by modern standards. Unfortunately we are stuck with it (well SystemVerilog) until tool vendors support something else.

    It's kind of a similar situation to JavaScript actually. And in a similar way, you can compile to Verilog, but just like with JS it makes debugging much more painful.

    There was this interesting project but it seems inactive: https://llhd.io/

    There's also various alternative HDLs that seem to have various levels of solving the wrong problem (SpinalHDL, MyHDL, Chisel). This one looks quite interesting though: https://filamenthdl.com/

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  • retroclash-lib

    Library code for upcoming RetroClash book

  • yieldfsm

    YieldFSM, a DSL for describing finite state machines in Clash

  • HDL_Converter

    A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

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Index

What are some of the best open-source hardware-description-language projects? This list will help you:

Project Stars
1 clash-ghc 1,375
2 awesome-hdl 881
3 PipelineC 544
4 systemrdl-compiler 222
5 kami 139
6 koika 128
7 filament 126
8 retroclash-lib 9
9 yieldfsm 8
10 HDL_Converter 5

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