asic-design

Open-source projects categorized as asic-design
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Language: + SystemVerilog + Python + VHDL + Coq
Topics: Fpga risc-v Axi4 Riscv Asic
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Top 7 asic-design Open-Source Projects

  • Cores-VeeR-EH1

    VeeR EH1 core

  • qkeras

    QKeras: a quantization deep learning library for Tensorflow Keras

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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  • VeriGPU

    OpenSource GPU, in Verilog, loosely based on RISC-V ISA

  • Cores-VeeR-EL2

    VeeR EL2 Core

  • neoTRNG

    🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

    • Project mention: A really tiny and platform-independent true random number generator for FPGAs and ASICs | /r/cryptography | 2023-11-06

  • deepsocflow

    An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

  • friscv

    RISCV CPU implementation in SystemVerilog

  • SaaSHub

    SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

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Index

What are some of the best open-source asic-design projects? This list will help you:

Project Stars
1 Cores-VeeR-EH1 773
2 qkeras 522
3 VeriGPU 484
4 Cores-VeeR-EL2 222
5 neoTRNG 152
6 deepsocflow 36
7 friscv 15

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