zerosoc
Verilog.jl
| zerosoc | Verilog.jl | |
|---|---|---|
| 2 | 2 | |
| 49 | 46 | |
| - | - | |
| 7.2 | 0.0 | |
| 2 months ago | about 7 years ago | |
| SystemVerilog | Julia | |
| - | GNU General Public License v3.0 or later |
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zerosoc
Verilog.jl
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Compiling Code into Silicon
It doesn't have to be. I once made a julia->verilog transpiler that even recompiled your julia functions with verilator, so you could verify that the code was correct.
https://github.com/interplanetary-robot/Verilog.jl
Of course, gaining traction on something like this is tricky.
I actually think Erlang/BEAM would be a great choice for making EDA tools, because it has concurrent execution model that you could probably very easily make play nice in rudimentary simulations of circuits that have triggers (`always @` sort of stuff.
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Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
A long long long time ago, I wrote this (currently very unmaintained) julia project, don't know if this is useful to you, but it's pretty clear that there is a LOT of potential for julia in this domain: https://github.com/interplanetary-robot/Verilog.jl
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Octavian.jl - Multi-threaded BLAS-like library that provides pure Julia matrix multiplication
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
myhdl - The MyHDL development repository
svls - SystemVerilog language server
gssi - Stuff I worked on while at GSSI (L'Aquila, Italy)
Modia.jl - Modeling and simulation of multidomain engineering systems
chisel - Chisel: A Modern Hardware Design Language
Automa.jl - A julia code generator for regular expressions