zerosoc
Demo SoC for SiliconCompiler. (by siliconcompiler)
gssi
Stuff I worked on while at GSSI (L'Aquila, Italy) (by lou1306)
| zerosoc | gssi | |
|---|---|---|
| 2 | 1 | |
| 49 | 3 | |
| - | - | |
| 7.2 | 10.0 | |
| about 1 month ago | over 5 years ago | |
| SystemVerilog | TeX | |
| - | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
zerosoc
Posts with mentions or reviews of zerosoc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-12-07.
gssi
Posts with mentions or reviews of gssi.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-12-07.
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Compiling Code into Silicon
Personally I have fond memories of MyHDL [0], which may be seen as another "code-to-silicon" converter (or at least as the first step of a code-to-silicon workflow). I used it only briefly, and on a school project that had surprisingly little to do with actual hardware design [1], but it really felt "Pythonic" in the best possible way.
[0]: https://www.myhdl.org/
[1]: https://github.com/lou1306/gssi/tree/master/2pc
What are some alternatives?
When comparing zerosoc and gssi you can also consider the following projects:
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Verilog.jl - Verilog for Julia
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
myhdl - The MyHDL development repository
chisel - Chisel: A Modern Hardware Design Language
edalize - An abstraction library for interfacing EDA tools
opentitan - OpenTitan: Open source silicon root of trust