verilog-axis
Verilog AXI stream components for FPGA implementation (by alexforencich)
verilog-axi
Verilog AXI components for FPGA implementation (by ZipCPU)
| verilog-axis | verilog-axi | |
|---|---|---|
| 7 | 2 | |
| 656 | 4 | |
| - | - | |
| 6.2 | 1.3 | |
| 19 days ago | over 3 years ago | |
| Python | Verilog | |
| MIT License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verilog-axis
Posts with mentions or reviews of verilog-axis.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-19.
- VIO core automation
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Constraints tied to a single module?
Another alternative is to use a Tcl script with a foreach, like it's done here: https://github.com/alexforencich/verilog-axis/blob/master/syn/vivado/sync_reset.tcl That file can be added the the list of constraint files in Vivado
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Any cons of replacing AXI-Stream Xilinx IPs with open-source (alexforencich) IPs
I'm grateful to find these open-source RTL IPs of u/alexforencich [AXIS modules: repo]. And they seem like a straightforward replacement to the following Xilinx IPs.
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How to compute log2 of non-constant logic variable?
Also FYI some FPGA tools have issues with recursive modules. This style can be unrolled, though. See https://github.com/alexforencich/verilog-axis/blob/master/rtl/priority_encoder.v
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Converting an FPGA design to ASIC
Xilinx soft IPs: I use the Xilinx IPs: AXI DMA, AXI-Stream Datawidth converter, AXI-Stream Clock converter...etc, for which I'm able to find open source RTL designs here, here and here.
- Looking for feedback on a simple parameterized bus module (verilog) I created to make it easier for me to build 8bit CPU designs
- Can an AXI stream FIFO IP remove bubbles from the input stream?
verilog-axi
Posts with mentions or reviews of verilog-axi.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-07-19.
-
Converting an FPGA design to ASIC
Xilinx soft IPs: I use the Xilinx IPs: AXI DMA, AXI-Stream Datawidth converter, AXI-Stream Clock converter...etc, for which I'm able to find open source RTL designs here, here and here.
-
Fast, open-source RTL IPs for fixed & floating-point multiplication, accumulation & conversion
I'm thinking of synthesizing it with ASIC tools such as Synopsys DesignCompiler to check the area & timing. I found some open source projects with Verilog IPs for AXI (zipcpu, alexforencich) and AXIS (alexforencich) modules, and I think I can replace the Xilinx IPs with them. After publishing my paper, I'm planning to release my code as open-source as well.
What are some alternatives?
When comparing verilog-axis and verilog-axi you can also consider the following projects:
verilog-axi - Verilog AXI components for FPGA implementation