uhd
corundum
uhd | corundum | |
---|---|---|
3 | 28 | |
918 | 1,478 | |
1.5% | 2.7% | |
9.5 | 9.0 | |
7 days ago | 6 days ago | |
Verilog | Verilog | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
uhd
- USRP Low Band Center Frequency Shift
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Adding patches upstream
Go upstream and first check that your work hasn't already been done. It is common for users to find bugs in a release and fix them, so it might already be patched or have a pull request. If not, go ahead and read/follow the coding and contributing docs.
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[OC] Visualizing the header/symbol dependencies on a single Cpp source file (out of 733 total C/C++ source code files in framework)
There's over 2000 files related to C/C++ software in this framework alone. The amount of organization, effort, and planning it takes to create large frameworks like this is hard to dismiss. Files can easily be in the thousands of lines long, at each little node on the screen.
corundum
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum
- Open sourceCorundum – FPGA-based NIC and platform for in-network compute
- TCP checksum computation
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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xilinx versal gty testbench/data gen?
Well, I did build this: https://github.com/corundum/corundum
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FPGA for finance industry
I would look into 10GbE PCS/MAC packet processors implemented under AXI Stream interfaces for example. There are open source examples https://github.com/corundum/corundum and https://netfpga.org/ .
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Computer Networking Nerd and EE Student Looking to build a Baremetal Network Driver on top of baremetal kernel? Is this possible and if so, I'd like some guidance!
I built my own 100 Gbps capable NIC, along with driver: https://github.com/corundum/corundum. You're welcome to ask if you have any questions, though it is quite a different animal from a 100 Mbps NIC you might have on a microcontroller.
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Device Drivers for Transceiver Questions (Specifically, PCIe)
If you're looking for resources, here's one rather comprehensive example of a high-performance FPGA design with a fully custom DMA engine and driver, that runs on both Xilinx and Intel FPGAs: https://github.com/corundum/corundum
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shift/concatenate in v/sv
I have no idea, but you're welcome to build the design and look at it yourself: https://github.com/corundum/corundum/tree/master/fpga/mqnic/NetFPGA_SUME/fpga. The barrel shifters are in the DMA engine, both the read DMA and write DMA engines have wide barrel shifters.
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Open source projects?
Dive right into the slack channel and introduce yourself. There is also a new contributor guide. /u/alexforencich/ is on these reddits and he may be able to chime in and give you more concrete suggestions.
What are some alternatives?
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
verilog-ethernet - Verilog Ethernet components for FPGA implementation
riscv - RISC-V CPU Core (RV32IM)
rssguard - Feed reader (and podcast player) which supports RSS/ATOM/JSON and many web-based feed services.
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
NvChad - Blazing fast Neovim config providing solid defaults and a beautiful UI, enhancing your neovim experience.
hdl - HDL libraries and projects
litex - Build your hardware, easily!
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
BYU_PYNQ_PR_Video_Pipeline - The Demo that was presented at FCCM.
hls4ml - Machine learning on FPGAs using HLS