sv2v
clash-ghc
| sv2v | clash-ghc | |
|---|---|---|
| 3 | 33 | |
| 470 | 1,372 | |
| - | 0.9% | |
| 7.6 | 9.1 | |
| 8 days ago | 6 days ago | |
| Haskell | Haskell | |
| BSD 3-clause "New" or "Revised" License | BSD 2-clause "Simplified" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
sv2v
-
Verilog functions and wires
I see what you mean by some online examples adding begin...end in functions. They are not actually required, and many people choose to leave it out (sv2v, lowRISC, BSG). I don't believe there is a benefit to adding them, and it just creates more opportunities for bugs that compilers/linters cannot check.
-
HDL desugaring
For verilog, I know SV2V exists: https://github.com/zachjs/sv2v
-
Unrolling Verilog generate statements
Maybe this would help? https://github.com/zachjs/sv2v
clash-ghc
- Clash: A Functional Hardware Description Language
- Clash (Haskell) for ASIC design
-
Building a Networked Key-Value-Store on an FPGA
> You'd be better off with a higher-level or more modern HDL that compiles to Verilog/VHDL. "Chisel" is one such.
As is Clash :) https://clash-lang.org/
-
Need project idea
You can take a look at https://clash-lang.org/. There is also a book for it. https://gergo.erdi.hu/retroclash/
-
5 layered CNN implementation on arduino/FPGAs [P]
I don't know much about FPGAs, but Clash lang compiles to VHDL, and might do the trick: https://clash-lang.org
- An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
- Pedagogical Downsides of Haskell
- Ask HN: Choice of HDL for an FPGA Project
-
Baud rate 1.5% lower than expected, is this normal?
if you need inspiration there is a full UART core available in clash: https://github.com/clash-lang/clash-compiler/blob/master/clash-cores/src/Clash/Cores/UART.hs
-
A circuit simulator that doesn't look like it was made in 2003
Perhaps peripheral (the original site has been hugged to death).
Both clashlang: https://clash-lang.org/
And Hardcaml: https://github.com/janestreet/hardcaml
have personally fueled my interest in hardware.
Dan Luu speaks eloquently and at length about how better options are needed for logic design. I would recommend both of the above to the enthusiastic novice.
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
wiringPi - A Haskell binding to the wiringPi library, for using GPIO on the Raspberry Pi.
conversion - Universal converter between values of different types
clash-prelude
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
mercury-api - Haskell binding to Mercury API for ThingMagic RFID readers
ICFP2020_Bluespec_Tutorial - Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
amaranth - A modern hardware definition language and toolchain based on Python
verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
hidapi - Haskell HIDAPI bindings
clash-prelude-quickcheck - QuickCheck instances for various types in the CλaSH Prelude