lion
clash-ghc
Our great sponsors
| lion | clash-ghc | |
|---|---|---|
| 10 | 33 | |
| 242 | 1,372 | |
| 0.8% | 1.6% | |
| 4.5 | 9.1 | |
| 5 days ago | 5 days ago | |
| Haskell | Haskell | |
| BSD 3-clause "New" or "Revised" License | BSD 2-clause "Simplified" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
lion
-
A year of RISC-V adventures: embracing chaos in your software journey [video]
I've been starting to dabble with digital logic design via Clash (https://clash-lang.org/), and there is a very cool-looking RISC-V SoC project done in that tool that looks fairly serious: https://github.com/standardsemiconductor/lion.
-
C++ Concurrency Model on x86 for Dummies
That’s fascinating about the M1. In retrospect it seems like kind of a no-brainer but I doubt I would have thought of it.
SPARC had different memory models at different ISA revs IIRC: it’s been like 20 years since I was dealing with SPARC so I might be misremembering the details. Alpha would have been a better example.
RISC-V is really interesting. I’ve been slowly working through this: https://github.com/standardsemiconductor/lion, highly recommend!
-
Why More Networks Should Imitate Cardano When It Comes To Writing And Shipping Code | Bitcoinist.com
Interesting. Actually, you may be just the person to answer my question: Is it possible/plausible to run a Cardano node on Lion OS on a RISC-V machine? IMO, it would be great for the community if we could run all Cardano stake pools on end to end formally verified machines using open source core and hardware.
- Lion is a formally verified, 5-stage pipeline RISC-V core
- Lion: A formally verified, 5-stage pipeline RISC-V core
-
Hacker News top posts: Mar 4, 2021
Lion: A formally verified, 5-stage pipeline RISC-V core\ (30 comments)
-
Where Lions Roam: RISC-V on the VELDT
In addition, you can actually set the riscv-formal suite to verify correctness by k-induction: https://github.com/SymbioticEDA/riscv-formal/pull/28 https://symbiyosys.readthedocs.io/en/latest/quickstart.html#beyond-bounded-model-checks although I concur that by looking at https://github.com/standardsemiconductor/lion/blob/main/lion-formal/app/Main.hs the lion core is only verified with BMC.
clash-ghc
- Clash: A Functional Hardware Description Language
- Clash (Haskell) for ASIC design
-
Building a Networked Key-Value-Store on an FPGA
> You'd be better off with a higher-level or more modern HDL that compiles to Verilog/VHDL. "Chisel" is one such.
As is Clash :) https://clash-lang.org/
-
Need project idea
You can take a look at https://clash-lang.org/. There is also a book for it. https://gergo.erdi.hu/retroclash/
-
5 layered CNN implementation on arduino/FPGAs [P]
I don't know much about FPGAs, but Clash lang compiles to VHDL, and might do the trick: https://clash-lang.org
- An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
- Pedagogical Downsides of Haskell
- Ask HN: Choice of HDL for an FPGA Project
-
Baud rate 1.5% lower than expected, is this normal?
if you need inspiration there is a full UART core available in clash: https://github.com/clash-lang/clash-compiler/blob/master/clash-cores/src/Clash/Cores/UART.hs
-
A circuit simulator that doesn't look like it was made in 2003
Perhaps peripheral (the original site has been hugged to death).
Both clashlang: https://clash-lang.org/
And Hardcaml: https://github.com/janestreet/hardcaml
have personally fueled my interest in hardware.
Dan Luu speaks eloquently and at length about how better options are needed for logic design. I would recommend both of the above to the enthusiastic novice.
What are some alternatives?
prometheus-cpp - Prometheus Client Library for Modern C++
wiringPi - A Haskell binding to the wiringPi library, for using GPIO on the Raspberry Pi.
riscv-formal - RISC-V Formal Verification Framework
clash-prelude
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
mercury-api - Haskell binding to Mercury API for ThingMagic RFID readers
atomic-story - Understanding how atomics and memory ordering work
ICFP2020_Bluespec_Tutorial - Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
libcxx - Project moved to: https://github.com/llvm/llvm-project
amaranth - A modern hardware definition language and toolchain based on Python