potato VS neorv32-riscof

Compare potato vs neorv32-riscof and see what are their differences.

potato

A simple RISC-V processor for use in FPGA designs. (by skordal)

neorv32-riscof

βœ”οΈPort of RISCOF to check the NEORV32 for RISC-V ISA compatibility. (by stnolting)
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potato neorv32-riscof
1 2
245 24
- -
0.0 9.1
over 1 year ago 1 day ago
VHDL Python
BSD 3-clause "New" or "Revised" License BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

potato

Posts with mentions or reviews of potato. We have used some of these posts to build our list of alternatives and similar projects.

neorv32-riscof

Posts with mentions or reviews of neorv32-riscof. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing potato and neorv32-riscof you can also consider the following projects:

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

riscv-debug-dtm - πŸ› JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

fpu - IEEE 754 floating point library in system-verilog and vhdl

neorv32-setups - πŸ“ NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.