riscv-profiles
linux-on-litex-vexriscv
riscv-profiles | linux-on-litex-vexriscv | |
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21 | 13 | |
87 | 536 | |
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8.0 | 5.2 | |
19 days ago | 12 days ago | |
Makefile | Python | |
Creative Commons Attribution 4.0 | BSD 2-clause "Simplified" License |
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riscv-profiles
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How to improve the RISC-V specification
Ssstrict is supposed to address the undefined behaviour problem, or at least it'll make undefined instructions actually trap.
https://github.com/riscv/riscv-profiles/blob/main/rva23-prof...
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Raspberry Pi receives strategic investment from Arm
>there are a lot of incompatible ISA implementations of RISC-V
This is common FUD.
In reality, most chips in the market, including all known application processors, follow the RVA profile[0] spec.
So do Linux distributions.
0. https://github.com/riscv/riscv-profiles/releases
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You Won’t Believe This One Weird CPU Instruction (2019)
The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1].
You can already buy SOCs that support it, e.g. vision five 2 and star64.
Interestingly the risc-v vector has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.
Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction.
[0] https://github.com/riscv/riscv-bitmanip/releases/download/1....
[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
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The legend of "x86 CPUs decode instructions into RISC form internally"
That's why we have RISC-V profiles.
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Why is std::hardware_destructive_interference_size a compile-time constant instead of a run-time value?
Yeah more or less. They now have RISC-V Application Profiles which are basically minimum requirements for "application processors" - essentially devices like phones where you might want to distribute binary apps.
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RISC-V Profiles: Defining sets of extensions for coherent ecosystems
The Profiles spec which includes RVA22 was finally ratified[0] last week.
0. https://github.com/riscv/riscv-profiles/releases/tag/v1.0
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RISC-V Profiles
Context: RISC-V profiles spec got ratified last week.
- Questions about standard extensions
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RISC-V Business: Testing StarFive's VisionFive 2 SBC
Yeah unfortunately there isn't really a great place that lists all the extensions with links and ratification status.
But anyway there is a sort of standard set of extensions that "application processors" (I guess CPUs that want to run precompiled code) should support:
https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
The 22 indicates the year.
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TinyEMU – x86 and RISC-V emulator, small and simple while being complete
Ah, you're right: https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
That's good to see. (Boy, it's really hard to find info about RISC-V profiles on Google. It just seems to ignore all the letters and numbers.)
linux-on-litex-vexriscv
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Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
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Education board tips
Hello, we are planning to rebuild a computer architectures course at uni and the idea is to teach the basics using the riscv architecture. We are looking for an affordable development board that could be used to demonstrate both bare-metal programming as well as interfacing hardware via mmap from OS to build up the experience with accessing the registers directly, and then introducing virtual memory, memory hierarchy, etc. So far it seems like a best option to utilize some compatible FPGA development board and the litex ( https://github.com/litex-hub/linux-on-litex-vexriscv ) project to achieve the afforementioned. Would you have any comment on that or perhaps some other recommendation for an affordable development board? Thanks for any tips.
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RISC-V Business: Testing StarFive's VisionFive 2 SBC
The repo below has support for building a 32bit RISC-V CPU for de10nano. It also includes information about booting Linux.
https://github.com/litex-hub/linux-on-litex-vexriscv
The CPU will likely have a clock speed around 100Mhz, far slower than the 1.5Ghz 64bit cores on the VisionFive 2 or Pi4. The FPGA might still be useful if you want to customize the CPU or integrate other custom hardware.
- Linux on LiteX
- Building RISCV that can eventually run Linux OS
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CosmicStrand: The discovery of a sophisticated UEFI firmware rootkit
You can run linux even on an entirely open source from hardware to software toolchain: https://github.com/litex-hub/linux-on-litex-vexriscv
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FPGA
On the other hand, if you really want a budget FPGA board under 100 USD that can implement a Linux-capable RISC-V SoC, you will need to implement a simple 32-bit one but indeed possible. See https://github.com/litex-hub/linux-on-litex-vexriscv for instance. You will get additional frequencies (still an order of 100 MHz though), I/O ports and such if you can spend 200 to 300 USD.
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Best fpga for making multicore linux-capable SoC?
An Artix 7 100k (like in the 'big' Arty A7 board) will comfortably fit 4 VexRiscv @ 100 MHz in a Litex SoC with all the bells and whistles; you can already fit a SoC with 2 Vex in the smaller 35k. Running Linux on that is very easy.
- Is it possible to build a RISCV Core on FPGA which runs Linux on top of it?
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Why has the barrier to entry for hardware design in general reduced so slowly?
Accessibility has improved significantly over the last few years. You can now buy any of the Lattice iCE40 or ECP5 boards from this page and use the yosys open-source workflow to upload real designs to the cores, including soft cores capable of running real, unmodified Linux. These tools are actively developed and are used by the open-source FPGA community at large (with the iCE40 and ECP5 receiving massive upticks in mindshare as a result).
What are some alternatives?
riscv-platform-specs - RISC-V Profiles and Platform Specification
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
xuantie-yocto - Yocto project for Xuantie RISC-V CPU
linux-on-litex-rocket - Run 64-bit Linux on LiteX + RocketChip
openc906 - OpenXuantie - OpenC906 Core
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
butterstick-hardware - Basic ECP5 based GigE to SYZYGY interface.
volk - The Vector Optimized Library of Kernels
UPduino-v3.0 - UPduino 3.0: new 4 layer layout, various other improvements
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
nmigen-tutorial - A tutorial for using nmigen