riscv-elf-psabi-doc
riscv-asm-manual
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riscv-elf-psabi-doc
- ARM64EC (and ARM64X) Explained
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Lazarus IDE 3.0 Released
Sure. It's the section here https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/ma...
It's that structs of two simple fields need to be passed in registers. And more specifically that this rule is relevant for mixed integer and floating point fields.
It's a very specific rule that requires a ton of code to implement compared to the integer calling convention. And again like the weird AMD64 convention likely invented to squeeze out a theoretical few cycles that never occur outside microbenchmarks
- Please help!
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RISC-V assembler input file format
This one has more info on the ELF output, notably things like how things like relocations and special symbols like %pcrel_hi work: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
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RISC-V assembly example: incrementing each char in a string
This is a bit dense but that's what I referred to https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc. I'm not sure if there's a RISC-V specific assembly tutorial that talks about calling conventions.
- RISCV on the rise. Intel joins the bandwagon. Threat or potential for linux gaming?
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RV32I Stack and stack pointer in hardware implementation
The stack is defined by the ABI and it’s a purely software convention. It’s possible a program could use a different convention. FYI, the EBI is defined here: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
- If you were to start your coding journey from zero, what would be your plan?
- Need reaources to learn Assembly
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Support for Extension and CSR detection in ELF and linker/loader?
It looks like people are starting to think somewhat along that direction in https://github.com/riscv-non-isa/riscv-elf-psabi-doc etc. but most CPUs that I can think of have basically a monolithic ISA with pretty much an expanding set of instructions as the versions increment and encoded in the -march argument to the linker.
riscv-asm-manual
- RISC-V Assembler: Arithmetic
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RISC-V assembler input file format
This document has most of the explanations about the input format: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md. There are some small missing bits but all the directives like .text are there.
- If you were to start your coding journey from zero, what would be your plan?
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Question about RISC-V development
The is a C and C++ toolchain available https://github.com/riscv-collab/riscv-gnu-toolchain If you feeling brave, https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md
- Is there any documentation relates to the riscv-gnu-toolchain ?
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Examples of RISC-V Assembly Programs
> Note: "jalr zero, 1b" can also be written as "j 1b", "jalr zero, 0(ra)" can be written as "ret"
`j` and `ret` are so-called "pseudo instructions" [1], not compressed instructions.
Pseudo instructions are just shortcuts used in assembly language to pretend that some common operations really "exist" with the need to type (or display) the real, more complex instructions. `nop` is a common pseudo instruction. RISC-V has `nop` instructions, but, instead, the "do nothing instruction" is canonically encoded as `addi x0, x0, 0`.
The compressed instruction set (a.k.a "extension C") is a subset of the full [2] instruction set, in which a restricted combinations of operands are possible. The assembly (human readable) code of the compressed instruction set looks similar to that of the full instruction set (including pseudo instructions), but they are encoded as completely different binary sequences.
[1] https://github.com/riscv/riscv-asm-manual/blob/master/riscv-...
[2] https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf#...
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RISCV Assembly and absolute addressing ?
This should be helpful https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md
- Absolute beginner to RISC-V, where do I start?
What are some alternatives?
riscv-isa-manual - RISC-V Instruction Set Manual
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
open-source-cs - Video discussing this curriculum:
glibc - GNU Libc
curriculum - The open curriculum for learning web development
computer-science - :mortar_board: Path to a free self-taught education in Computer Science!
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
picocli - Picocli is a modern framework for building powerful, user-friendly, GraalVM-enabled command line apps with ease. It supports colors, autocompletion, subcommands, and more. In 1 source file so apps can include as source & avoid adding a dependency. Written in Java, usable from Groovy, Kotlin, Scala, etc.
arduino-6502ctl - Arduino 6502 Controller
osblog - The Adventures of OS