riscv-elf-psabi-doc
riscv-isa-manual
riscv-elf-psabi-doc | riscv-isa-manual | |
---|---|---|
11 | 41 | |
633 | 3,282 | |
1.7% | 2.3% | |
7.1 | 9.7 | |
9 days ago | 5 days ago | |
Python | TeX | |
Creative Commons Attribution 4.0 | Creative Commons Attribution 4.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-elf-psabi-doc
- ARM64EC (and ARM64X) Explained
-
Lazarus IDE 3.0 Released
Sure. It's the section here https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/ma...
It's that structs of two simple fields need to be passed in registers. And more specifically that this rule is relevant for mixed integer and floating point fields.
It's a very specific rule that requires a ton of code to implement compared to the integer calling convention. And again like the weird AMD64 convention likely invented to squeeze out a theoretical few cycles that never occur outside microbenchmarks
- Please help!
-
RISC-V assembler input file format
This one has more info on the ELF output, notably things like how things like relocations and special symbols like %pcrel_hi work: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
-
RISC-V assembly example: incrementing each char in a string
This is a bit dense but that's what I referred to https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc. I'm not sure if there's a RISC-V specific assembly tutorial that talks about calling conventions.
- RISCV on the rise. Intel joins the bandwagon. Threat or potential for linux gaming?
-
RV32I Stack and stack pointer in hardware implementation
The stack is defined by the ABI and it’s a purely software convention. It’s possible a program could use a different convention. FYI, the EBI is defined here: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
- If you were to start your coding journey from zero, what would be your plan?
- Need reaources to learn Assembly
-
Support for Extension and CSR detection in ELF and linker/loader?
It looks like people are starting to think somewhat along that direction in https://github.com/riscv-non-isa/riscv-elf-psabi-doc etc. but most CPUs that I can think of have basically a monolithic ISA with pretty much an expanding set of instructions as the versions increment and encoded in the -march argument to the linker.
riscv-isa-manual
-
The Improved RISC-V Specification (latest WIP draft)
https://github.com/riscv/riscv-isa-manual/releases
Regarding the recent "How to improve the RISC-V specification" post [0], I just wanted to point out, that the latest draft manual is already a great improvement. (see link above)
It includes a lot of the newly ratified extensions: bitmanip,zicond,vector,vector crypto, ...
And there are a bunch of included SAIL definitions for bitmanip and zicond, but other instructions are still missing the SAIL code. Most notably, the SAIL definitions from the RV32I/RV64I base isa are also missing.
I asked for the further SAIL integration plans here: https://github.com/riscv/riscv-isa-manual/issues/1369
Here is an example SAIL snippet from cpopw:
let bitcount = 0;
-
How to improve the RISC-V specification
I encourage you to look at the newest isa manual draft on github: https://github.com/riscv/riscv-isa-manual/releases
It includes the more recently extensions, and e.g. the bitmanip instructions all have associated pseudo code.
Here is e.g. the code for cpopw:
let bitcount = 0;
- Need help with designing a basic RISC V processor?
-
The legend of “x86 CPUs decode instructions into RISC form internally”
I tried searching the spec [1] for "overflow" and here is what it says at page 17:
> We did not include special instruction-set support for overflow checks on integer arithmetic operations in the base instruction set, as many overflow checks can be cheaply implemented using RISC-V branches.
> For general signed addition, three additional instructions after the addition are required
Is this "cheap", replacing 1 instruction with four? According to some old mainframe era research (cannot find link now), addition is the most often used instruction and they suggest that we should replace each one with four?
Their "rationale" is not rational at all. It doesn't make sense.
Overflow check should be free (no additional instructions required), otherwise we will see the same story we have seen for last 50 years: compiler writers do not want to implement checks because they are expensive; language designers do not want to use proper arithmetic because it is expensive. As a result, there will be errors and vulnerabilities. A vicious circle.
[1] https://github.com/riscv/riscv-isa-manual/releases/download/...
- 64-bit Arm ∩ 64-bit RISC V
- Beginner question: F extension
-
Riscv Ghidra Instruction Manual
Why not use the actual release PDF instead from their github? https://github.com/riscv/riscv-isa-manual
-
How would I go about designing an 8-bit RISC-V CPU? Is it possible?
https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf Part 2
-
Have to convert a C language code into RISC-V MIPS
If you don't want to cheat then read the RISC-V ISA manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
-
How does a computer understand machine language?
Yeah you are on the right track. Processors are designed on top of an Instruction Set Architecture (ISA). For an example you can look on top of the RISC-V specifications:https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf (possible PDF download)
What are some alternatives?
open-source-cs - Video discussing this curriculum:
riscv-emulator-docker-image
curriculum - The open curriculum for learning web development
amaranth - A modern hardware definition language and toolchain based on Python
computer-science - :mortar_board: Path to a free self-taught education in Computer Science!
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
riscv-asm-manual - RISC-V Assembly Programmer's Manual
vroom - VRoom! RISC-V CPU
picocli - Picocli is a modern framework for building powerful, user-friendly, GraalVM-enabled command line apps with ease. It supports colors, autocompletion, subcommands, and more. In 1 source file so apps can include as source & avoid adding a dependency. Written in Java, usable from Groovy, Kotlin, Scala, etc.
osblog - The Adventures of OS
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.