riscv-asm-manual
arduino-6502ctl
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|---|---|---|
| 8 | 3 | |
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| Creative Commons Attribution 4.0 | MIT License |
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riscv-asm-manual
- RISC-V Assembler: Arithmetic
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RISC-V assembler input file format
This document has most of the explanations about the input format: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md. There are some small missing bits but all the directives like .text are there.
- If you were to start your coding journey from zero, what would be your plan?
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Question about RISC-V development
The is a C and C++ toolchain available https://github.com/riscv-collab/riscv-gnu-toolchain If you feeling brave, https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md
- Is there any documentation relates to the riscv-gnu-toolchain ?
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Examples of RISC-V Assembly Programs
> Note: "jalr zero, 1b" can also be written as "j 1b", "jalr zero, 0(ra)" can be written as "ret"
`j` and `ret` are so-called "pseudo instructions" [1], not compressed instructions.
Pseudo instructions are just shortcuts used in assembly language to pretend that some common operations really "exist" with the need to type (or display) the real, more complex instructions. `nop` is a common pseudo instruction. RISC-V has `nop` instructions, but, instead, the "do nothing instruction" is canonically encoded as `addi x0, x0, 0`.
The compressed instruction set (a.k.a "extension C") is a subset of the full [2] instruction set, in which a restricted combinations of operands are possible. The assembly (human readable) code of the compressed instruction set looks similar to that of the full instruction set (including pseudo instructions), but they are encoded as completely different binary sequences.
[1] https://github.com/riscv/riscv-asm-manual/blob/master/riscv-...
[2] https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf#...
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RISCV Assembly and absolute addressing ?
This should be helpful https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md
- Absolute beginner to RISC-V, where do I start?
arduino-6502ctl
What are some alternatives?
riscv-elf-psabi-doc - A RISC-V ELF psABI Document
riscv-isa-manual - RISC-V Instruction Set Manual
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
glibc - GNU Libc
open-source-cs - Video discussing this curriculum:
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
computer-science - :mortar_board: Path to a free self-taught education in Computer Science!
curriculum - The open curriculum for learning web development
riscv-c-api-doc - Documentation of the RISC-V C API
nasm - A cross-platform x86 assembler with an Intel-like syntax