riscv-asm-manual VS riscv-elf-psabi-doc

This document has most of the explanations about the input format: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md. There are some small missing bits but all the directives like .text are there.

The is a C and C++ toolchain available https://github.com/riscv-collab/riscv-gnu-toolchain If you feeling brave, https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md

> Note: "jalr zero, 1b" can also be written as "j 1b", "jalr zero, 0(ra)" can be written as "ret"

`j` and `ret` are so-called "pseudo instructions" [1], not compressed instructions.

Pseudo instructions are just shortcuts used in assembly language to pretend that some common operations really "exist" with the need to type (or display) the real, more complex instructions. `nop` is a common pseudo instruction. RISC-V has `nop` instructions, but, instead, the "do nothing instruction" is canonically encoded as `addi x0, x0, 0`.

The compressed instruction set (a.k.a "extension C") is a subset of the full [2] instruction set, in which a restricted combinations of operands are possible. The assembly (human readable) code of the compressed instruction set looks similar to that of the full instruction set (including pseudo instructions), but they are encoded as completely different binary sequences.

[1] https://github.com/riscv/riscv-asm-manual/blob/master/riscv-...

[2] https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf#...

This should be helpful https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md

Sure. It's the section here https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/ma...

It's that structs of two simple fields need to be passed in registers. And more specifically that this rule is relevant for mixed integer and floating point fields.

It's a very specific rule that requires a ton of code to implement compared to the integer calling convention. And again like the weird AMD64 convention likely invented to squeeze out a theoretical few cycles that never occur outside microbenchmarks

This one has more info on the ELF output, notably things like how things like relocations and special symbols like %pcrel_hi work: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc

This is a bit dense but that's what I referred to https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc. I'm not sure if there's a RISC-V specific assembly tutorial that talks about calling conventions.

The stack is defined by the ABI and it’s a purely software convention. It’s possible a program could use a different convention. FYI, the EBI is defined here: https://github.com/riscv-non-isa/riscv-elf-psabi-doc

It looks like people are starting to think somewhat along that direction in https://github.com/riscv-non-isa/riscv-elf-psabi-doc etc. but most CPUs that I can think of have basically a monolithic ISA with pretty much an expanding set of instructions as the versions increment and encoded in the -march argument to the linker.