risc-v_pipelined_cpu
qtrvsim
| risc-v_pipelined_cpu | qtrvsim | |
|---|---|---|
| 1 | 1 | |
| 0 | 412 | |
| - | 4.1% | |
| 10.0 | 8.9 | |
| about 1 year ago | 5 days ago | |
| SystemVerilog | C++ | |
| - | GNU General Public License v3.0 only |
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risc-v_pipelined_cpu
-
How a CPU works: Bare metal C on my RISC-V toy CPU
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu
qtrvsim
-
How a CPU works: Bare metal C on my RISC-V toy CPU
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu
What are some alternatives?
fpga-experiments
Astro8-Computer - Custom 16-bit homebrew CPU, emulator, renderer, circuit, and language
Digital - A digital logic designer and circuit simulator.
Kite - Kite: Architecture Simulator for RISC-V Instruction Set
cs2410 - An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh.
Ripes - A graphical processor simulator and assembly editor for the RISC-V ISA