risc-v_pipelined_cpu VS Digital

- source & native releases: https://github.com/cvut/qtrvsim

It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.

I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu

Theres the open source Digital (https://github.com/hneemann/Digital) which can run simulations but then export Verilog. If you have an ICE40 based GPU then in theory you can then use open source tools (like apio) to get that onto your FPGA. I've seen some impressive fpga tasks being generated by that.

I'm early in my learning of FPGA and have done nandgame and some other non-HDL circuit learnings. I have gone back and forth if I want to design my project via HDL or via something like Digital. There's not an easy pro/con either way.

Used the recommended JRT https://adoptium.net/

Wandered through the https://github.com/hneemann/Digital site and saw past issues with JRT but no obvious solution.

I have a couple hundred GALs of same or similar model number of new old stock

Check if https://github.com/hneemann/Digital and/or Logisim are for you.

someone posted a logic gate graph some days ago which sent me through a loop of remaking a 4bit multiplier i designed in Digital Logic, in desmos. unfortunately everything is pretty much explicitly defined and put together as to maintain only the appearance of this exact circuit, so theres no ui for placing components drawing wires and building your own circuits. yet ;]

This is my favorite book and I read it while trying to create the circuits myself before learning the chapter using digital - it's very enlightening and I recommend you do the same

Digital

The Digital application can generate a circuit based on a truth table. An example...