risc-v-single-cycle
A Single Cycle Risc-V 32 bit CPU (by martinKindall)
Arithmetic-Circuits
This repository contains different modules which execute arithmetic operations. (by GabbedT)
risc-v-single-cycle | Arithmetic-Circuits | |
---|---|---|
1 | 1 | |
21 | 3 | |
- | - | |
10.0 | 3.8 | |
about 1 year ago | 8 months ago | |
SystemVerilog | SystemVerilog | |
- | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
risc-v-single-cycle
Posts with mentions or reviews of risc-v-single-cycle.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-12-26.
-
My first Risc-V core in FPGA
Code is here: https://github.com/martinKindall/risc-v-single-cycle
Arithmetic-Circuits
Posts with mentions or reviews of Arithmetic-Circuits.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Vivado doesn't generate flip flops
This is the entire code if you need to look: https://github.com/GabbedT/Arithmetic-Circuits/blob/main/Integer/Multipliers/pipelined_long_multiplier.sv
What are some alternatives?
When comparing risc-v-single-cycle and Arithmetic-Circuits you can also consider the following projects:
learn-fpga - Learning FPGA, yosys, nextpnr, and RISC-V
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
mips_cpu - Single Cycle 32 bit MIPS
Cores-VeeR-EH1 - VeeR EH1 core
basys3_fpga_sandbox - Learning the basics of Systemverilog, testbench and more.