pymtl3
magma
pymtl3 | magma | |
---|---|---|
5 | 3 | |
350 | 238 | |
2.3% | - | |
4.6 | 8.6 | |
7 days ago | about 1 month ago | |
Python | Python | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
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pymtl3
- Firrtl – Flexible Intermediate Representation for RTL
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Why are there only 3 languages for FPGA development?
Also PyMTL, PyRTL, and MyHDL.
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Choice of Python HDL library
PyMTL
- RISC-V reference model in Python
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Tools for designing hardware in Python
Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
magma
What are some alternatives?
myhdl - The MyHDL development repository
rohd - The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
PyRTL - A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
hVHDL_example_project - An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
hVHDL_fixed_point - VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.
hVHDL_floating_point - high level VHDL floating point library for synthesis in fpga
migen - A Python toolbox for building complex digital hardware
firrtl - Flexible Intermediate Representation for RTL