clic
RISC-V fast interrupt controller (by pulp-platform)
VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA (by hughperkins)
| clic | VeriGPU | |
|---|---|---|
| 1 | 2 | |
| 16 | 484 | |
| - | - | |
| 2.3 | 0.0 | |
| 27 days ago | about 1 year ago | |
| SystemVerilog | SystemVerilog | |
| Apache License 2.0 | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
clic
Posts with mentions or reviews of clic.
We have used some of these posts to build our list of alternatives
and similar projects.
VeriGPU
Posts with mentions or reviews of VeriGPU.
We have used some of these posts to build our list of alternatives
and similar projects.
What are some alternatives?
When comparing clic and VeriGPU you can also consider the following projects:
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Cores-VeeR-EL2 - VeeR EL2 Core
Cores-VeeR-EH1 - VeeR EH1 core
riscv-simple-sv - A simple RISC V core for teaching
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
ulm-on-ice - ULM (Ulm Lecture Machine) on ice40