ara
esp
| ara | esp | |
|---|---|---|
| 5 | 1 | |
| 304 | 297 | |
| 2.0% | 2.0% | |
| 7.5 | 7.5 | |
| 21 days ago | 14 days ago | |
| C | C | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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ara
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x86 vs ARM; Vector and Matrix Extensions; How do they compare?
yeah, ara also currently doesn't work, but that it exist is already really cool, and will likely get fixed and completed in the future
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Ara2: RVV 1.0 Compliant Open-Source Processor
The ISA is variable length/scalable, but this implementation uses a 4096 wide register file.
They are a bit disingenuous in claiming they support rvv 1.0 while others only a subset, as they haven't implemented vrgather or vcompress yet, but there are open pull request for them [0].
Sadly there also seem to be a few bugs when simulating with verilator [1], so I couldn't measure all instructions, but here is `vadd.vv` and `vwaddu.vv` for the VLEN=4096, four lane configuration:
vadd.vv:
e32m1: 16 cycles
e32m2 32 cycles
e32m4 63 cycles
e32m8 126 cycles
vwaddu.vv:
e32m1: 34 cycles
e32m2: 69 cycles
e32m4: 140 cycles
[0] https://github.com/pulp-platform/ara/pull/180
[1] https://github.com/pulp-platform/ara/issues/250
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432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space
The PULP Ara is a 64-bit Vector Unit
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Iām not expert, but I guess it is worth to check out
It's not made very clear until the Conclusion section that they have provided an open source implementation of a RVV 1.0 vector unit, available at https://github.com/pulp-platform/ara : "The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core."
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Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
esp
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
What are some alternatives?
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
rosetta - Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
simd_utils - A header only library implementing common mathematical functions using SIMD intrinsics
Vitis-HLS-Introductory-Examples
snitch - ā DEPRECATED ā Lean but mean RISC-V system!
Vitis-Tutorials - Vitis In-Depth Tutorials
riscv-ocelot - Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
Unicorn Engine - Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
litex - Build your hardware, easily!
mempool - A 256-RISC-V-core system with low-latency access into shared L1 memory.