esp
mempool
| esp | mempool | |
|---|---|---|
| 1 | 2 | |
| 297 | 229 | |
| 2.0% | 2.2% | |
| 7.5 | 9.0 | |
| 24 days ago | 6 days ago | |
| C | C | |
| GNU General Public License v3.0 or later | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
esp
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
mempool
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MemPool: Many-core image processor based on RISC-V with Shared L1 cache
I don't get it:
https://github.com/pulp-platform/mempool/blob/main/software/...
How is that mapping to cores happening? I see indexing by core id for the multiply but how does it magically end up running on a specific core? Magic compiler?
What are some alternatives?
ara - The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rosetta - Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Vitis-HLS-Introductory-Examples
rt-thread - RT-Thread is an open source IoT real-time operating system (RTOS).
Vitis-Tutorials - Vitis In-Depth Tutorials
RVVM - The RISC-V Virtual Machine
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
esp32_usb_soft_host - ESP32 software USB host through general IO pins. We can connect up to 4 USB-LS HID (keyboard mouse joystick) devices simultaneously.
litex - Build your hardware, easily!