ara
Unicorn Engine
ara | Unicorn Engine | |
---|---|---|
5 | 14 | |
304 | 7,168 | |
2.0% | 0.9% | |
7.5 | 1.0 | |
21 days ago | 2 days ago | |
C | C | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ara
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x86 vs ARM; Vector and Matrix Extensions; How do they compare?
yeah, ara also currently doesn't work, but that it exist is already really cool, and will likely get fixed and completed in the future
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Ara2: RVV 1.0 Compliant Open-Source Processor
The ISA is variable length/scalable, but this implementation uses a 4096 wide register file.
They are a bit disingenuous in claiming they support rvv 1.0 while others only a subset, as they haven't implemented vrgather or vcompress yet, but there are open pull request for them [0].
Sadly there also seem to be a few bugs when simulating with verilator [1], so I couldn't measure all instructions, but here is `vadd.vv` and `vwaddu.vv` for the VLEN=4096, four lane configuration:
vadd.vv:
e32m1: 16 cycles
e32m2 32 cycles
e32m4 63 cycles
e32m8 126 cycles
vwaddu.vv:
e32m1: 34 cycles
e32m2: 69 cycles
e32m4: 140 cycles
[0] https://github.com/pulp-platform/ara/pull/180
[1] https://github.com/pulp-platform/ara/issues/250
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432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space
The PULP Ara is a 64-bit Vector Unit
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I’m not expert, but I guess it is worth to check out
It's not made very clear until the Conclusion section that they have provided an open source implementation of a RVV 1.0 vector unit, available at https://github.com/pulp-platform/ara : "The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core."
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Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
Unicorn Engine
- Unicorn: Lightweight multi-platform, multi-architecture CPU emulator framework
- 86Box v4.0
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Show HN: Tetris, but the blocks are ARM instructions that execute in the browser
OFRAK Tetris is a project I started at work about two weeks ago. It's a web-based game that works on desktop and mobile. I made it for my company to bring to events like DEF CON, and to promote our binary analysis and patching framework called OFRAK.
In the game, 32-bit, little-endian ARM assembly instructions fall, and you can modify the operands before executing them on a CPU emulator. There are two segments mapped – one for instructions, and one for data (though both have read, write, and execute permissions). Your score is a four byte signed integer stored at the virtual address pointed to by the R12 register, and the goal is to use the instructions that fall to make the score value in memory as high as possible. When it's game over, you can download your game as an ELF to relive the glory in GDB on your favorite ARM device.
The CPU emulator is a version of Unicorn (https://www.unicorn-engine.org/) that has been cross-compiled to WebAssembly (https://alexaltea.github.io/unicorn.js/), so everything on the page runs in the browser without the need for any complicated infrastructure on the back end.
Since I've only been working on this for a short period of time leading up to its debut at DEF CON, there are still many more features I'd eventually like to implement. These include adding support for other ISAs besides ARM, adding an instruction reference manual, and lots of little cleanups, bug fixes, and adjustments.
My highest score is 509,644,979, but my average is about 131,378.
I look forward to feedback, bug reports, feature requests, and strategy discussions!
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It Takes 6 Days to Change 1 Line of Code
Entails hundreds of hours of single-stepping through that opcode in Linux kernel using an indirect operand pointing toward its own opcode (self-modifying code).
Even the extraordinaire Fabrice Bellard (author of QEMU) admitted that it is broke and did a total rewrite, which fixed tons of other issues.
https://github.com/unicorn-engine/unicorn/issues/364
- FOSS Simulator for debugging C code (even better if it supports some MCUs)
- Unicorn: Lightweight multi-platform, multi-architecture CPU emulation framework
- Unicorn - CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
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Vita3K android running Tales of Hearts R - A Glimpse of What's to come
Macdu (Vita3K dev) also stated that this game is CPU bound so they used a CPU emulator known as unicorn2 , this is also the reason for the slow speed
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QEMU Version 7.0.0 Released
This is how I found out a snippet of assembly code that can actually distinguished between a KVM hypervisor and most of today’s emulator.
https://github.com/unicorn-engine/unicorn/issues/364
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Top Python Tools for Malware Analysis. – PythonStacks
Unicorn is missing from that list.
The python CPU emulator with full program counter (PC) and general (and other CPU-specific) register set controls.
I use it to catch fileless malware in the second fastest dynamic manner. Also good for detecting Rowhammer/SPECTRE behaviors.
Disclaimer: one of the contributors and a contractor that frequently deploy this.
https://github.com/unicorn-engine/unicorn
What are some alternatives?
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
QEMU - Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
simd_utils - A header only library implementing common mathematical functions using SIMD intrinsics
MicroPython - MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
capstone - Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings. [Moved to: https://github.com/capstone-engine/capstone]
snitch - ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
Reverse-Engineering-Tutorial - A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit ARM & 64-bit ARM architectures.
riscv-ocelot - Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
TinyVM - TinyVM is a small, fast, lightweight virtual machine written in pure ANSI C.
box86 - Box86 - Linux Userspace x86 Emulator with a twist, targeted at ARM Linux devices
qemu-t8030 - iPhone 11 emulated on QEMU