prjtrellis
chisel
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prjtrellis | chisel | |
---|---|---|
5 | 25 | |
381 | 3,717 | |
0.0% | 2.3% | |
8.5 | 9.7 | |
3 months ago | 3 days ago | |
Python | Scala | |
GNU General Public License v3.0 or later | Apache License 2.0 |
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prjtrellis
- Project Trellis – Documenting the Lattice ECP5 FPGA Bitstream Format
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Learning Verilog and FPGA
Yosys, the underlying compiler of ice studio, also targets the much bigger ECP5 FPGA, also by Lattice, which is called Project Trellis: https://github.com/YosysHQ/prjtrellis
Yosys functions more like a software open source tool. So command line compiling. It also has a REPL. It is very quick compared to the commercial solutions. Especially around compile times which can take seconds instead of minutes. YMMV, but I think the consensus is that it's a lot more convenient to use.
In general the hardware toolchains feel very ancient compared to software toolchains.
- Project Trellis – fully open-source flow for ECP5 FPGAs, using Yosys and nextpnr
- 5% of 666 Python repos had comma typo bugs (inc V8, TensorFlow and PyTorch)
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Lattice ECP3 - any way of working withe them with free license ?
Not that it will lead to anything soon, you could put a feature request in at Project Trellis and offer to test things, or provide hardware if you have extra.
chisel
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Calyx: Intermediate Language for Hardware Accelerators
My first instinct was to ask "Does this play well with CIRCT?" And thankfully they answer that right away in the README.
I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.
That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."
A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.
There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].
1: https://www.chisel-lang.org
2: https://github.com/sarchlab/akita
- Chisel: A Modern Hardware Design Language
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I may be creating an abomination
Inspired by Scala. Which can do a whole lot more, and worse. The currently biggest competitor to decades old hardware description languages is a Scala DSL.
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An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
Already mentioned Chisel: https://www.chisel-lang.org/
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Trying to learn and work with FPGAs
I'm also a hobbyist. There are a number of alternative HDLs out there, and as hobbyists we can deviate more from the mainstream of (System)Verilog and VHDL if we desire, though you'll still need to be able to read them. In the past I've done Verilog, but lately I've been using SpinalHDL and have been really enjoying it. Its close relative Chisel also makes appearances in the RISC-V space.
- Alternate HDL language and Physical Design/EDA tools?
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Learning VDHL after knowing Verilog
What are your thoughts on other HDLs like Chisel or BlueSpec when it comes to better type checking?
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Learning Verilog and FPGA
I started playing with FPGAs and HDLs a couple years ago with no hardware design background (I'm mostly a software architect/engineer) and in the end found that a "higher-level" HDL suited me better.
I chose Chisel (https://www.chisel-lang.org/) an HDL based on Scala (technically a Scala DSL) which can provide many facilities to hardware generation.
I'd highly advise looking into it although also knowing Verilog helps a lot.
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If you keep clicking "Give 15 seconds" on Lichess, eventually it overflows to a negative number and you win
But some go further and ask "what if when we add a soldering station on top of it?"
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What universities have good PhD programmes in digital design?
In recent years Chisel HDL, RISC V, and SiFive came out of their architecture group, to name a few.
What are some alternatives?
Vulkan-ValidationLayers - Vulkan Validation Layers (VVL)
SpinalHDL - Scala based HDL
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
myhdl - The MyHDL development repository
quickstep - Quickstep project
amaranth - A modern hardware definition language and toolchain based on Python
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
apio - :seedling: Open source ecosystem for open FPGA boards
bsc - Bluespec Compiler (BSC)