pico-png
surf
| pico-png | surf | |
|---|---|---|
| 1 | 1 | |
| 15 | 285 | |
| - | 1.1% | |
| 6.6 | 8.7 | |
| about 1 month ago | 7 days ago | |
| VHDL | VHDL | |
| Mozilla Public License 2.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
pico-png
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How useful has CocoTB been for you?
The only publicly available project example I have, is a small png encoder with this parametrization and this testbench. However this is draft code, since VUnit + GHDL is used on the main branch. (VUnit might be also an alternative if your team uses VHDL or Systemverilog.)
surf
What are some alternatives?
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
cocotb-test - Unit testing for cocotb
chisel - Chisel: A Modern Hardware Design Language
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
tiny-cores - Collection of assorted small cores
pocket-cnn - CNN-to-FPGA-framework for small CNN, written in VHDL and Python
basejump_stl - BaseJump STL: A Standard Template Library for SystemVerilog
Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.
fusesoc-cores - FuseSoC standard core library
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development