openwifi VS cva6

There is some open source firmware for very old WiFi chips:

https://wiki.debian.org/Firmware/Open#Radio

There is also some FPGA based open source WiFi chip things:

https://github.com/open-sdr/openwifi

https://news.ycombinator.com/item?id=27133079 :

https://ans.unibs.it/projects/csi-murder/ enabled by https://github.com/open-sdr/openwifi Both partially funded by EU's Horizon2020 program.

Openwifi talk at FOSDEM 2020 https://www.youtube.com/watch?v=8q5nHUWP43U

one of the developments out of his openwifi project is a 'Openwifi CSI fuzzer WiSec21 demo interview' https://www.youtube.com/watch?v=Jp2ImjCnlkQ

https://github.com/open-sdr/openwifi/blob/master/doc/app_not...

You could try the Xilinx ZC706 with an ADI9361 based FMCOMMS board. The OpenWIFI team has a few configurations listed on their readme that are popular: https://github.com/open-sdr/openwifi. I think these setups will still cost >$1000USD and require considerable effort to get going - I don’t know of a <$1000 SDR setup for 5G development that would be easy to setup and get going with. Curious if anyone knows of one.

Nice one Nuand, the BladeRF v2 looks like a very interesting alternative SDR modem to the cheaper Adalm Pluto educational kit by Analog Devices, the manufacturer of the transceiver chip being used by the BladeRF v2.

There is another alternative open source WiFi stack, openwifi and it has been discussed in HN before [2][3].

[1]https://www.analog.com/en/design-center/evaluation-hardware-...

[2 ]https://github.com/open-sdr/openwifi

[3]https://news.ycombinator.com/item?id=24273919

Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)

The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.

I made a post about this here not too long ago, but I think it would be really useful to come up with a Vivado benchmark, in the form of a standardized large and representative design. I was curious about Alder Lake performance too, and compared my new 12700K workstation against my laptop with this open source RISC-V CPU: https://github.com/openhwgroup/cva6

When the OpenHW Group was created in 2019, I had some hope that Alibaba or NXP (who are in the OpenHW Group) would release an open hardware RISC-V processor, but it looks like they are not making any public commits to the CVA6 core, so I doubt that we are ever going to see the source code of Alibaba's XT910 or NXP's Chassis RISC-V processor.

Ariane is now cva6 (it moved to a industry supported non-profit).

At this stage, it could make sense for e.g. universities to start developing peripherals & controllers targeted at ASIC rather than creating yet-another-core (https://riscv.org/exchange/cores-socs/ has 107 lines already for cores), leveraging an OSHW ASIC-proven core from e.g. the OpenHW group (https://github.com/openhwgroup/cva6). Manufacturing in not-so-old processes is affordable for teaching institutions (e.g. https://europractice-ic.com/ in Europe), and taping out working cores is no longer a 'new' thing (e.g. http://asic.ethz.ch/all/years.html ).

Looking at the github of the openhw group looks like the license is granting patents to the project. So it looks ok.