openc906
microwatt
openc906 | microwatt | |
---|---|---|
14 | 19 | |
285 | 643 | |
1.1% | - | |
1.3 | 6.7 | |
12 months ago | 22 days ago | |
Verilog | Verilog | |
Apache License 2.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
openc906
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Milk-V Duo: A $9 RISC-V COMPUTER
Datasheet: https://github.com/milkv-duo/hardware
Reading the datasheet, it looks like there is one C906 cpu with 700 Mhz without the the vector extension and one C906 cpu at 1Ghz with rvv 0.7.1. The C906 design has been opensourced and is available here: https://github.com/T-head-Semi/openc906
The C906 supports rv64gc with optimal rvv 0.7.1 with a vlen of 128, but a 256 wide ALU.
They list H.264/H.265 support, but I don't think it's a standardized extension.
But see my other comment about using the pre ratification vector extension:
- New RISC-V SoCs. Are they private and secure, or just more of the same?
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ARM versus RISC-V
Note that the implementations themselves are often not open source, for example a random person won't be able to get the sources of these SiFive cores anywhere. As of a open-source core from a commercial company, the OpenC906 is an open-source implementation provided by T-Head, but the vector unit is not included in the open source version and thus cannot enabled.
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Core2Duo doesnt have backdoor
Still not free hardware, real chads use XuanTie C906 based MangoPi MQ-PRO!
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Google wants RISC-V to be a “tier-1” Android architecture
Try and see if you can find any stolen code here[0] or here[1].
Cheers.
0. https://github.com/T-head-Semi/openc906
1. https://github.com/T-head-Semi/openc910
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RISC-V Pushes into the Mainstream
I wouldn't quite say that's the case. Two of the three full Linux capable RISC-V SoC releases this year are using open source CPU cores. The BL808 and the Allwinner D1 both use T-Head CPU cores that are available on GitHub https://github.com/T-head-Semi/openc906 . The JH7110 in the VisionFive2 and Star 64 does use a closed CPU core however.
- Store access fault when executing AMO instructions in Nezha D1
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Does a truly secure Linux system exist?
For example, let's take the ClockworkPi uConsole. It uses an Allwinner D1 chip as it's main processor which has a seemingly auditable XuanTie C906 which could theoretically be verified if one opened up a few chips.
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Buying RISC-V development board
For an example of what CPU core RTL looks like look no further than: https://github.com/T-head-Semi/openc906
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Packed-SIMD (P) vs Vector (V) extension
For example, for the record, the open source C906 RTL, found here https://github.com/T-head-Semi/openc906 doesn't even have the vector files in there.
microwatt
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Microwatt: A tiny Open POWER ISA softcore written in VHDL 2008
My favorite part of this project is the pretty large battery of test cases. A lot of chip rtl releases don't bother with open sourcing the verification too, and that's arguably more useful than the rtl in the first place.
https://github.com/antonblanchard/microwatt/tree/master/test...
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Arm wants to charge dramatically more for chip licenses
MicroWatt is the only one I know of.
https://github.com/antonblanchard/microwatt
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RISC-V Pushes into the Mainstream
I have several OpenPOWER systems, including the POWER9 I use as my usual desktop. Besides IBM and other server manufacturers like Tyan and Wistron, you can get them as Raptor workstations and servers.
If you want an OpenPOWER design to play with, look at Microwatt ( https://github.com/antonblanchard/microwatt ) which is complete enough to boot Linux.
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How long until RISC gets adopted for the desktop?
Not true, as of 2019 the power ISA is able to be used without needing to pay any royalties to ibm under the openpower foundation. There's already a few projects that have taken advantage of it such as libreSOC and Microwatt. Source code for various firmware components are also freely available pertaining to the power platform.
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Build Open Silicon with Google
https://github.com/antonblanchard/microwatt is an example of a Linux-capable 64-bit core that has been submitted on multiple Open MPW shuttles:
- Any raw binary generic platform-agnostic test roms for PowerPC?
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What would you think if the Amiga line jumped from PowerPc to RISC-V CPUs?
GitHub https://github.com/openpower-cores https://github.com/antonblanchard/microwatt
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Keeping POWER relevant in the open source world
At the other end of the scale, if anyone wants to play you can run a little openpower CPU on a FPGA with completely open source. https://github.com/antonblanchard/microwatt
It's capable of running Linux, some example docs are https://shenki.github.io/boot-linux-on-microwatt/
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What is your take on ISA architectures for FPGAs (x86, arm, risc-v)?
Why dismiss POWER or SPARC ? :-)
What are some alternatives?
openc910 - OpenXuantie - OpenC910 Core
chiselwatt - A tiny POWER Open ISA soft processor written in Chisel
aosp-riscv - Patches & Script for AOSP to run on Xuantie RISC-V CPU [Moved to: https://github.com/T-head-Semi/riscv-aosp]
midimonster - Multi-protocol control & translation software (ArtNet, MIDI, OSC, sACN, ...)
xuantie-yocto - Yocto project for Xuantie RISC-V CPU
Apollo-11 - Original Apollo 11 Guidance Computer (AGC) source code for the command and lunar modules.
riscv-profiles - RISC-V Architecture Profiles
OpenSkyStacker - Multi-platform stacker for deep-sky astrophotography.
riscv-aosp - Patches & Script for AOSP to run on Xuantie RISC-V CPU
VexRiscvBPluginGenerator
linux - Patches include sunxi platform support and various driver fixes
librealsense - Intel® RealSense™ SDK