openc906 VS vroom

Datasheet: https://github.com/milkv-duo/hardware

Reading the datasheet, it looks like there is one C906 cpu with 700 Mhz without the the vector extension and one C906 cpu at 1Ghz with rvv 0.7.1. The C906 design has been opensourced and is available here: https://github.com/T-head-Semi/openc906

The C906 supports rv64gc with optimal rvv 0.7.1 with a vlen of 128, but a 256 wide ALU.

They list H.264/H.265 support, but I don't think it's a standardized extension.

But see my other comment about using the pre ratification vector extension:

Note that the implementations themselves are often not open source, for example a random person won't be able to get the sources of these SiFive cores anywhere. As of a open-source core from a commercial company, the OpenC906 is an open-source implementation provided by T-Head, but the vector unit is not included in the open source version and thus cannot enabled.

Still not free hardware, real chads use XuanTie C906 based MangoPi MQ-PRO!

Try and see if you can find any stolen code here[0] or here[1].

Cheers.

0. https://github.com/T-head-Semi/openc906

1. https://github.com/T-head-Semi/openc910

I wouldn't quite say that's the case. Two of the three full Linux capable RISC-V SoC releases this year are using open source CPU cores. The BL808 and the Allwinner D1 both use T-Head CPU cores that are available on GitHub https://github.com/T-head-Semi/openc906 . The JH7110 in the VisionFive2 and Star 64 does use a closed CPU core however.

For example, let's take the ClockworkPi uConsole. It uses an Allwinner D1 chip as it's main processor which has a seemingly auditable XuanTie C906 which could theoretically be verified if one opened up a few chips.

For an example of what CPU core RTL looks like look no further than: https://github.com/T-head-Semi/openc906

For example, for the record, the open source C906 RTL, found here https://github.com/T-head-Semi/openc906 doesn't even have the vector files in there.

Maybe implement a big feature for a open source design? like vroom or xiangshan.

The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.

I had VROOM! in mind (https://github.com/MoonbaseOtago/vroom) because I remembered it aims for 4 IPC avg with a width of 8. Though looking again it's 8 compressed 16 bit instructions or 4 uncompressed 32 bit instruction.

So you could argue a real mix of instructions is not going to be all 16 bit but some 16 and some 32, so the 8 is rarely achieved in practice, and also the block diagram only shows 4 decode blocks. But it can in fact peak at 8 instructions decoded per clock, so I think that qualifies. (You could even argue it's especially impressive, since RISC-V technically qualifies as variable-length encoding like x86, it's just that only 16/32 instructions are really used at the moment)

If you are interested in high performance look into vroom , c910 and xianghan, maybe you could adopt one of them.

On top of what others mentioned (Red Hat) , it is also possible to go with the mysql/mariadb model of dual licensing, you can have a copyleft license where you must contribute back changes, but also allow selling an proprietary license if they want to enhance it but not share the improvements (like amazon or Ampere Computing that enhance ARM designs and sells it for servers), there is already a RISK-V implementation that aims to do that (vroom). another option is a non profit foundation that companies contribute to because they use the project and want it to be better (like the linux foundation) , risc-v has similar nonprofits like the chips alliance (which develops the Rocket-Chip ) or the OpenHW Group (which develops CVA6), there is also lowrisc which develops ibex (but as far as i can tell isn't governed by the contributing companies like the other non profits).

You want a very optimistic answer? someone is working on open source server core, It is already announced and i have been told it is somewhere around four years for a chip to ship after announcement so i would say 4 years from now.

At the moment the Apple M1/M2 are the king of wide decode. Within a couple of years you will see equally wide decode and execute of RISC-V from companies such as Rivos, or indeed open source and GPL'd projects such as VROOM! (https://github.com/MoonbaseOtago/vroom)

> True performance RISCV designs are going to be people's money maker and never open sourced.

That turns out not to be the case.

Alibaba's C910 core -- roughly comparable to the ARM A72 cores (at the same MHz) in the Pi 4 -- is open sourced. It is being used, at 2.5 GHz, in the upcoming "Roma" laptop. That is rather expensive (for now), but I suspect the same TH1520 SoC will quickly find its way onto cheaper SBCs.

There is a very wide OoO GPL'd RISC-V core that is under development. It is aiming for eventual Apple M1 level performance. The current iteration is falling short of that at the moment, but it's already comparable to the ARM A76 in the latest RK3588 SBCs: https://github.com/MoonbaseOtago/vroom

Then you can help open source hardware designs like xiangshan or vroom.