vroom | openc910 | |
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17 | 42 | |
447 | 1,047 | |
- | 2.0% | |
5.0 | 1.3 | |
9 months ago | 5 months ago | |
Verilog | Verilog | |
GNU General Public License v3.0 only | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
vroom
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How can I leverage RISC-V in my final year Electrical & Electronics Engineering project? Seeking advice and project ideas.
Maybe implement a big feature for a open source design? like vroom or xiangshan.
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In your opinion, what is the most advanced open source softcore processor?
The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.
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ARM or x86? ISA Doesn’t Matter
I had VROOM! in mind (https://github.com/MoonbaseOtago/vroom) because I remembered it aims for 4 IPC avg with a width of 8. Though looking again it's 8 compressed 16 bit instructions or 4 uncompressed 32 bit instruction.
So you could argue a real mix of instructions is not going to be all 16 bit but some 16 and some 32, so the 8 is rarely achieved in practice, and also the block diagram only shows 4 decode blocks. But it can in fact peak at 8 instructions decoded per clock, so I think that qualifies. (You could even argue it's especially impressive, since RISC-V technically qualifies as variable-length encoding like x86, it's just that only 16/32 instructions are really used at the moment)
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How to build a Startup use open source chips
If you are interested in high performance look into vroom , c910 and xianghan, maybe you could adopt one of them.
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ARM versus RISC-V
On top of what others mentioned (Red Hat) , it is also possible to go with the mysql/mariadb model of dual licensing, you can have a copyleft license where you must contribute back changes, but also allow selling an proprietary license if they want to enhance it but not share the improvements (like amazon or Ampere Computing that enhance ARM designs and sells it for servers), there is already a RISK-V implementation that aims to do that (vroom). another option is a non profit foundation that companies contribute to because they use the project and want it to be better (like the linux foundation) , risc-v has similar nonprofits like the chips alliance (which develops the Rocket-Chip ) or the OpenHW Group (which develops CVA6), there is also lowrisc which develops ibex (but as far as i can tell isn't governed by the contributing companies like the other non profits).
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When will there be a 16-32 core RISC V high end desktop processor and motherboard ?
You want a very optimistic answer? someone is working on open source server core, It is already announced and i have been told it is somewhere around four years for a chip to ship after announcement so i would say 4 years from now.
- Open-source RISC-V CPU projects for contribution
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What caused/started the "CISC vs RISC" in the 1980s?
At the moment the Apple M1/M2 are the king of wide decode. Within a couple of years you will see equally wide decode and execute of RISC-V from companies such as Rivos, or indeed open source and GPL'd projects such as VROOM! (https://github.com/MoonbaseOtago/vroom)
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ARM to prohibit proximity of CPU w 3rd-party modules in one chip
> True performance RISCV designs are going to be people's money maker and never open sourced.
That turns out not to be the case.
Alibaba's C910 core -- roughly comparable to the ARM A72 cores (at the same MHz) in the Pi 4 -- is open sourced. It is being used, at 2.5 GHz, in the upcoming "Roma" laptop. That is rather expensive (for now), but I suspect the same TH1520 SoC will quickly find its way onto cheaper SBCs.
There is a very wide OoO GPL'd RISC-V core that is under development. It is aiming for eventual Apple M1 level performance. The current iteration is falling short of that at the moment, but it's already comparable to the ARM A76 in the latest RK3588 SBCs: https://github.com/MoonbaseOtago/vroom
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I am bored because I am not capable to work and want to learn something useful/interesting
Then you can help open source hardware designs like xiangshan or vroom.
openc910
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US Government reportedly ponders crimping China's use of RISC-V
> I'm pretty sure that SiFive isn't allowed to sell their RISC-V core designs to any Chinese company already.
The JH7110 SoC from the Chinese firm Starfive uses SiFive's U74 core. Eswin, also Chinese uses SiFive's P550 core in their upcoming EIC7700 SoC.
> All Chinese RISC-V core designs have been proprietary designs thus far.
There is the OpenC910 [1] and OpenXiangShan [2].
[1] https://github.com/T-head-Semi/openc910
- Lichee Console 4A – RISC-V mini laptop: Review, benchmarks and early issues
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Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
Note that the C910 CPU cores used in this chip are in fact open source:
https://github.com/T-head-Semi/openc910
(C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)
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This CPU is FREE!
The Milk-V Pioneer uses a C910 CPU, which has been open sourced by t-head: https://github.com/T-head-Semi/openc910
- LTT
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China Deploys RISC-V Server in Commercial Cloud
More precisely, a Chinese university assembled a rack containing 48 [1] commercially available SBCs [2], each with a Chinese-designed and made SG2042 SoC with 64 C910 CPU cores. The C910 was designed in China in 2018/19 and open-sourced in October 2021, on Microsoft's github site.
https://github.com/T-head-Semi/openc910
The SG2042 is the most powerful RISC-V SoC available today.
In which direction is the technology transfer going?
[1] or possibly 24 dual-socket boards, shown at the RISC-V Summit China in August
[2] get your own here https://www.crowdsupply.com/milk-v/milk-v-pioneer
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Raspberry Pi receives strategic investment from Arm
For "coming down the pipeline" they're essentially free.
Today, the c910 is an Apache 2, hardware proven out of order core on GitHub here https://github.com/T-head-Semi/openc910 a little slower than an RPi3's core.
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Lichee Pi 4A: Serious RISC-V Desktop Computing [video]
Here is the source code* for the CPU:
https://github.com/T-head-Semi/openc910
* AFAIK they didn't opensource the pre ratification vector extension implementation they ship with the taped out chip.
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Beagleboard BeagleV-Ahead RISC-V brd released
The source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago.
https://github.com/T-head-Semi/openc910
The same cores are used in the 64 core SG2042 workstation/server SoC.
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ARM’s Cortex A53: Tiny but Important
It's a shame, because it was the best design from ARM; they're now focusing on Cortex-A7x and Cortex-X, which aren't anywhere as power efficient[0].
Meanwhile, their revised Cortex-A57 has been surpassed in performance/power/area by several RISC-V microarchitectures, such as SiFive's U74[1], used in the VisionFive2 and Star64, or even the open source XuanTie C910[2][3].
0. https://www.youtube.com/watch?v=s0ukXDnWlTY
1. https://www.sifive.com/cores/u74
2. https://xrvm.com/cpu-details?id=4056743610438262784
3. https://github.com/T-head-Semi/openc910
What are some alternatives?
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
XiangShan - Open-source high-performance RISC-V processor
openc906 - OpenXuantie - OpenC906 Core
riscv-isa-manual - RISC-V Instruction Set Manual
hn-search - Hacker News Search
aosp-riscv - Patches & Script for AOSP to run on Xuantie RISC-V CPU [Moved to: https://github.com/T-head-Semi/riscv-aosp]
seL4 - The seL4 microkernel
riscv-sbi-doc - Documentation for the RISC-V Supervisor Binary Interface
awesome-riscv - 😎 A curated list of awesome RISC-V implementations