nmigen-tutorial
RISCV-FiveStage
nmigen-tutorial | RISCV-FiveStage | |
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301 | 89 | |
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1.8 | 0.0 | |
about 3 years ago | over 3 years ago | |
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Creative Commons Attribution Share Alike 4.0 | Apache License 2.0 |
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nmigen-tutorial
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recommended free (open source) verification platform ?
nmigen-tutorial
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Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer
I've had this recommended and it looks v promising! https://vivonomicon.com/2020/04/14/learning-fpga-design-with...
Someone above has mentioned Robert Baruch too: https://github.com/RobertBaruch/nmigen-tutorial
I also found this helpful: http://blog.lambdaconcept.com/doku.php?id=nmigen:tutorial
And there is of course the IRC channel if you want to ask people questions, #nmigen on irc.freenode.net
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FPGA dev board that's cheap, simple and supported by OSS toolchain
If you are already familiar with Python I could recommend start with this tutorial: https://github.com/RobertBaruch/nmigen-tutorial
RISCV-FiveStage
- Tips on building a RISC-V processor on FPGA
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Planning to develop a CPU on an FPGA. How can I program it?
I can recommend the coursework that I made for my university. It uses chisel (similar to verilog but less finickity and annoying) to create a five stage RISC-V 32I capable processors that can run small bare metal programs. The intro: https://github.com/PeterAaser/tdt4255-chisel-intro The 5-stage: https://github.com/PeterAaser/RISCV-FiveStage
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Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer
It's coursework that takes you from knowing nothing about hardware design to designing your own RISC-V In-Order Five stage architecture. As far as I know a few students have actually done the work to run this on an FPGA, but for the most part you will have the luxury of an emulator, giving you things like stack traces compared to the model execution for all the test programs etc.
https://github.com/PeterAaser/RISCV-FiveStage
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Want to get started.What to buy?
If you want to do something big but simulated you can try to do this coursework https://github.com/PeterAaser/RISCV-FiveStage I made for my university, teaching CPU design. It's in chisel though, which is different from verilog. Be sure to look at the intro first.
What are some alternatives?
litex - Build your hardware, easily!
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
cortex-m0-soft-microcontroller - Soft-microcontroller implementation of an ARM Cortex-M0
apio - :seedling: Open source ecosystem for open FPGA boards
wyre - Hardware definition language that compiles to Verilog
tdt4255-chisel-intro
UPduino-v3.0 - UPduino 3.0: new 4 layer layout, various other improvements
icebreaker - Small and low cost FPGA educational and development board
dromajo - RISC-V RV64GC emulator designed for RTL co-simulation