ndk-app-minimal
forth-cpu
ndk-app-minimal | forth-cpu | |
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4 | 2 | |
23 | 315 | |
- | - | |
8.2 | 2.6 | |
17 days ago | about 2 years ago | |
VHDL | VHDL | |
BSD 3-clause "New" or "Revised" License | - |
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ndk-app-minimal
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A simple high-throughput open-source packet generator
as the title says, I'm looking to build a simple packet generator (a PCAP (re)player might be a better term), mainly for load-testing network devices. The goal is to be able to fully congest a 400G Ethernet line. To achieve such a high throughput rate, I plan to use the NDK platform to build my application.
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Xilinx alternatives??
We have few Intel Agilex I-Series FPGA boards in our lab. It can do 400G Ethernet 8x56Gb or 4x112Gb (F-Tile), PCIe Gen5 x16 (R-Tile) and CXL IP is for a fee, I think. You can find an example of using F/R-Tile in our open-source NDK: https://github.com/CESNET/ndk-app-minimal
- The Network Development Kit for FPGA cards in version 0.3.1 released
- The Network Development Kit for FPGA cards released as open-source
forth-cpu
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Designs targeting specific boards?
Like in my head I thought having a piece of verilog and having enough LUTs in any board would do the thing, so what meant here? An example https://github.com/howerj/forth-cpu mentions that the target board is a specific Xilinx.
- Forth SoC Written in VHDL
What are some alternatives?
projf-explore - Project F brings FPGAs to life with exciting open-source designs you can build on.
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
sdram-fpga - A FPGA core for a simple SDRAM controller.
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
VHDL-Guide - VHDL Guide
pocket-cnn - CNN-to-FPGA-framework for small CNN, written in VHDL and Python
Arcade_Galaga - Galaga Arcade Core
Flo-Posit - Posit Arithmetic Cores generated with FloPoCo
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components