litedram
openwifi
| litedram | openwifi | |
|---|---|---|
| 6 | 10 | |
| 359 | 3,566 | |
| - | 1.4% | |
| 6.4 | 7.3 | |
| about 1 month ago | 27 days ago | |
| Python | C | |
| GNU General Public License v3.0 or later | GNU Affero General Public License v3.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
litedram
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
I could be wrong, but I don't think the LiteX DRAM PHY is using the UG586 block. Here's the Litex Series 7 DRAM PHY source code - it appears to be hardcoding the PHY logic. The Lattice ECP5 code in that directory does the same thing.
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I am trying to avoid AXI Bus for DDR3 access on Arty A7
Try https://github.com/enjoy-digital/litedram with a RAW or FIFO interface. It is in Migen, a python DSL HDL, but you could just use the output.
- LiteDRAM – A fully open-source memory controller targeting LPDDR4/5 for FPGA
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Suggest advance project ideas
You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.
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How many more years until we have a completely open source RISC-V SOC?
So for instance (and AFAI understand...) the DDR2 sdram controller uses a generic PHY (https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/gensdrphy.py) , but the DDR3 one has to talk to some vendor-specific PHY (e.g. https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py ). The controller itself is vendor-agnostic (https://github.com/enjoy-digital/litedram/blob/master/litedram/core/controller.py). On Xilinx FPGA it doesn't rely on MIG at all.
openwifi
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Hold on there: WPA3 connections fail after 11 hours
There is some open source firmware for very old WiFi chips:
https://wiki.debian.org/Firmware/Open#Radio
There is also some FPGA based open source WiFi chip things:
https://github.com/open-sdr/openwifi
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WiFi: “beamforming” only begins to describe it (2014)
https://news.ycombinator.com/item?id=27133079 :
https://ans.unibs.it/projects/csi-murder/ enabled by https://github.com/open-sdr/openwifi Both partially funded by EU's Horizon2020 program.
Openwifi talk at FOSDEM 2020 https://www.youtube.com/watch?v=8q5nHUWP43U
- Tesla Coil Zenneck Wave TV White Space Wifi Network
- Any way to transmit 802.11(wifi) signals to a receiver
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Can 5G be used as surveillance radar? U.S. military funds Binghamton research
one of the developments out of his openwifi project is a 'Openwifi CSI fuzzer WiSec21 demo interview' https://www.youtube.com/watch?v=Jp2ImjCnlkQ
https://github.com/open-sdr/openwifi/blob/master/doc/app_not...
- Is there an intersection between FPGA and Wireless Comms?
- How many more years until we have a completely open source RISC-V SOC?
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Ask HN: How to get started with 5G as a software developer
You could try the Xilinx ZC706 with an ADI9361 based FMCOMMS board. The OpenWIFI team has a few configurations listed on their readme that are popular: https://github.com/open-sdr/openwifi. I think these setups will still cost >$1000USD and require considerable effort to get going - I don’t know of a <$1000 SDR setup for 5G development that would be easy to setup and get going with. Curious if anyone knows of one.
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BladeRF-wiphy: open-source IEEE 802.11 compatible Software Defined Radio modem
Nice one Nuand, the BladeRF v2 looks like a very interesting alternative SDR modem to the cheaper Adalm Pluto educational kit by Analog Devices, the manufacturer of the transceiver chip being used by the BladeRF v2.
There is another alternative open source WiFi stack, openwifi and it has been discussed in HN before [2][3].
[1]https://www.analog.com/en/design-center/evaluation-hardware-...
[2 ]https://github.com/open-sdr/openwifi
[3]https://news.ycombinator.com/item?id=24273919
What are some alternatives?
litex - Build your hardware, easily!
bladeRF-wiphy - bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
SpinalHDL - Scala based HDL
esp32-wifi-penetration-tool - Exploring possibilities of ESP32 platform to attack on nearby Wi-Fi networks.
litepcie - Small footprint and configurable PCIe core
SaxonSoc - SoC based on VexRiscv and ICE40 UP5K
gr-ieee802-11 - IEEE 802.11 a/g/p Transceiver
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
direwolf - Dire Wolf is a software "soundcard" AX.25 packet modem/TNC and APRS encoder/decoder. It can be used stand-alone to observe APRS traffic, as a tracker, digipeater, APRStt gateway, or Internet Gateway (IGate). For more information, look at the bottom 1/4 of this page and in https://github.com/wb2osz/direwolf/blob/dev/doc/README.md
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
ZynqMP-FPGA-Linux - FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)