litedram VS OpenSERDES

I could be wrong, but I don't think the LiteX DRAM PHY is using the UG586 block. Here's the Litex Series 7 DRAM PHY source code - it appears to be hardcoding the PHY logic. The Lattice ECP5 code in that directory does the same thing.

Try https://github.com/enjoy-digital/litedram with a RAW or FIFO interface. It is in Migen, a python DSL HDL, but you could just use the output.

You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.

So for instance (and AFAI understand...) the DDR2 sdram controller uses a generic PHY (https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/gensdrphy.py) , but the DDR3 one has to talk to some vendor-specific PHY (e.g. https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py ). The controller itself is vendor-agnostic (https://github.com/enjoy-digital/litedram/blob/master/litedram/core/controller.py). On Xilinx FPGA it doesn't rely on MIG at all.

But here is an open source ASIC-proven serdes block, [OpenSERDES](https://github.com/SparcLab/OpenSERDES). [Here's the paper describing it](https://arxiv.org/abs/2105.13256). It's only 2 Gb/s per link, but it seems like that would be enough to do DDR3. It is available on Skywater OpenPDK 130nm.