ice40_power
hdl
| ice40_power | hdl | |
|---|---|---|
| 2 | 5 | |
| 20 | 1,378 | |
| - | 2.0% | |
| 0.0 | 9.1 | |
| over 3 years ago | 7 days ago | |
| Verilog | Verilog | |
| MIT License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ice40_power
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iCE40 power consumption question
You can probably extrapolate from the numbers here.
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Using an FPGA for low-power device with fast image acquisition
Aside from the points that /u/captain_wiggles_ pointed out, this is an application which ice40 FPGAs were actually designed for. They are low power (example) and have some features specifically designed for video applications, such as (sub)LVDS inputs and "outputs." Depending on your specs, one of these FPGAs could be a good choice (and you get a nice FOSS toochain as a bonus).
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
What are some alternatives?
riscv - RISC-V CPU Core (RV32IM)
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
a2o - The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
uhd - The USRP™ Hardware Driver Repository
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
USB_C_Industrial_Camera_FPGA_USB3 - Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.