fsm2sv
SystemVerilog FSM generator (by mohamed)
teroshdl-documenter-demo
This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow. (by TerosTechnology)
| fsm2sv | teroshdl-documenter-demo | |
|---|---|---|
| 1 | 1 | |
| 21 | 10 | |
| - | - | |
| 0.6 | 0.0 | |
| 16 days ago | over 2 years ago | |
| Python | Python | |
| BSD 3-clause "New" or "Revised" License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fsm2sv
Posts with mentions or reviews of fsm2sv.
We have used some of these posts to build our list of alternatives
and similar projects.
teroshdl-documenter-demo
Posts with mentions or reviews of teroshdl-documenter-demo.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Open source FPGA/ASIC IDE: TerosHDL 2.0.0
I have added an example of the Documenter: https://github.com/TerosTechnology/teroshdl-documenter-demo It works with a lot of open source projects: https://terostechnology.github.io/teroshdl-documenter-demo/
What are some alternatives?
When comparing fsm2sv and teroshdl-documenter-demo you can also consider the following projects:
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
hdl_checker - Repurposing existing HDL tools to help writing better code
eda-log-file-warning-suppressor - Suppresses warnings in EDA logfiles.
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
edalize - An abstraction library for interfacing EDA tools