freepdk-45nm
gssi
| freepdk-45nm | gssi | |
|---|---|---|
| 1 | 1 | |
| 108 | 3 | |
| 0.0% | - | |
| 10.0 | 10.0 | |
| about 4 years ago | over 5 years ago | |
| Verilog | TeX | |
| - | GNU General Public License v3.0 or later |
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freepdk-45nm
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Compiling Code into Silicon
Pretty neat, a python tool that converts Verilog to an IC layout so that you can make your own custom SOC (assuming you have a substantial budget to pay for fab).
Since it's not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is "an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)" [0], ASAP7 "Warning Work in progress (not ready for use)" [1] and Skywater130 which "As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available." [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4]
If this sounds negative, it's not, I just couldn't figure out what processes this was intended for without digging. ASAP7 is Arm and NCSU, and Skywater130 is Skywater and Google.
[0] https://github.com/mflowgen/freepdk-45nm
gssi
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Compiling Code into Silicon
Personally I have fond memories of MyHDL [0], which may be seen as another "code-to-silicon" converter (or at least as the first step of a code-to-silicon workflow). I used it only briefly, and on a school project that had surprisingly little to do with actual hardware design [1], but it really felt "Pythonic" in the best possible way.
[0]: https://www.myhdl.org/
[1]: https://github.com/lou1306/gssi/tree/master/2pc
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Verilog.jl - Verilog for Julia
edalize - An abstraction library for interfacing EDA tools
opentitan - OpenTitan: Open source silicon root of trust
zerosoc - Demo SoC for SiliconCompiler.
chisel - Chisel: A Modern Hardware Design Language