fpga-experiments
qtrvsim
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| fpga-experiments | qtrvsim | |
|---|---|---|
| 1 | 1 | |
| 7 | 412 | |
| - | 14.8% | |
| 10.0 | 8.9 | |
| over 1 year ago | 3 days ago | |
| Python | C++ | |
| MIT License | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fpga-experiments
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How a CPU works: Bare metal C on my RISC-V toy CPU
You are right :)
Here's the repo: https://github.com/fnoeding/fpga-experiments
I'll update the post with it too.
qtrvsim
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How a CPU works: Bare metal C on my RISC-V toy CPU
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu
What are some alternatives?
risc-v_pipelined_cpu - RISC-V CPU with a 5-stage pipeline, written in SystemVerilog
Astro8-Computer - Custom 16-bit homebrew CPU, emulator, renderer, circuit, and language
Kite - Kite: Architecture Simulator for RISC-V Instruction Set
cs2410 - An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh.
Digital - A digital logic designer and circuit simulator.
Ripes - A graphical processor simulator and assembly editor for the RISC-V ISA