cyc1000-rsu
forth-cpu
cyc1000-rsu | forth-cpu | |
---|---|---|
1 | 2 | |
7 | 315 | |
- | - | |
4.1 | 2.6 | |
almost 3 years ago | about 2 years ago | |
VHDL | VHDL | |
MIT License | - |
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cyc1000-rsu
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Intel Cyclone 10 LP update from serial comm
Hi, there is my solution of CYC1000 (Cyclone 10 LP board) Remote System Upgrade. The first implementation allows remote bitstream updates via the UART interface. https://github.com/jakubcabal/cyc1000-rsu
forth-cpu
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Designs targeting specific boards?
Like in my head I thought having a piece of verilog and having enough LUTs in any board would do the thing, so what meant here? An example https://github.com/howerj/forth-cpu mentions that the target board is a specific Xilinx.
- Forth SoC Written in VHDL
What are some alternatives?
uart-for-fpga - Simple UART controller for FPGA written in VHDL
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
sdram-fpga - A FPGA core for a simple SDRAM controller.
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
VHDL-Guide - VHDL Guide
pocket-cnn - CNN-to-FPGA-framework for small CNN, written in VHDL and Python
Arcade_Galaga - Galaga Arcade Core
Flo-Posit - Posit Arithmetic Cores generated with FloPoCo
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components