clash-pong
clash-ghc
clash-pong | clash-ghc | |
---|---|---|
1 | 33 | |
9 | 1,375 | |
- | 1.2% | |
4.7 | 9.1 | |
16 days ago | 5 days ago | |
Tcl | Haskell | |
MIT License | BSD 2-clause "Simplified" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
clash-pong
-
Retrocomputing with Clash: Haskell for FPGA Hardware Design (book)
However, all the code from the book (as collected at https://retrocla.sh/) synthesizes for real hardware FPGAs. I've been using a Nexys A7-50T (Xilinx 7-series FPGA) and old Papilio Pro (Xilinx 6-series) and Papilio One (Xilinx 3-series) FPGAs; the Nexys is my daily driver so all repos come with Shake rules for building for that. But people have also contributed support for the DECA Arrow (Intel MAX 10) and Terasic DE0-Nano (Intel Cyclone IV) to clash-pong, so you should be able to take that as a template if you want to use something else.
clash-ghc
- Clash: A Functional Hardware Description Language
- Clash (Haskell) for ASIC design
-
Building a Networked Key-Value-Store on an FPGA
> You'd be better off with a higher-level or more modern HDL that compiles to Verilog/VHDL. "Chisel" is one such.
As is Clash :) https://clash-lang.org/
-
Need project idea
You can take a look at https://clash-lang.org/. There is also a book for it. https://gergo.erdi.hu/retroclash/
-
5 layered CNN implementation on arduino/FPGAs [P]
I don't know much about FPGAs, but Clash lang compiles to VHDL, and might do the trick: https://clash-lang.org
- An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
- Pedagogical Downsides of Haskell
- Ask HN: Choice of HDL for an FPGA Project
-
Baud rate 1.5% lower than expected, is this normal?
if you need inspiration there is a full UART core available in clash: https://github.com/clash-lang/clash-compiler/blob/master/clash-cores/src/Clash/Cores/UART.hs
-
A circuit simulator that doesn't look like it was made in 2003
Perhaps peripheral (the original site has been hugged to death).
Both clashlang: https://clash-lang.org/
And Hardcaml: https://github.com/janestreet/hardcaml
have personally fueled my interest in hardware.
Dan Luu speaks eloquently and at length about how better options are needed for logic design. I would recommend both of the above to the enthusiastic novice.
What are some alternatives?
Violet - Superscalar RISC-V processor written in Clash.
wiringPi - A Haskell binding to the wiringPi library, for using GPIO on the Raspberry Pi.
clashilator - Generate interface between Clash and Verilator
clash-prelude
basic-ecp5-pcb - Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
mercury-api - Haskell binding to Mercury API for ThingMagic RFID readers
clash-calculator - FPGA desktop calculator for seven-segment display and keypad, written in Clash
ICFP2020_Bluespec_Tutorial - Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
amaranth - A modern hardware definition language and toolchain based on Python
verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
hidapi - Haskell HIDAPI bindings