clash-pong VS clashilator

However, all the code from the book (as collected at https://retrocla.sh/) synthesizes for real hardware FPGAs. I've been using a Nexys A7-50T (Xilinx 7-series FPGA) and old Papilio Pro (Xilinx 6-series) and Papilio One (Xilinx 3-series) FPGAs; the Nexys is my daily driver so all repos come with Shake rules for building for that. But people have also contributed support for the DECA Arrow (Intel MAX 10) and Terasic DE0-Nano (Intel Cyclone IV) to clash-pong, so you should be able to take that as a template if you want to use something else.

Debugging via high-level simulation is something my book spends a lot of time on. If you look at the sample chapters, you can see that the same Clash code can also be compiled into software Haskell, which you can then interface with non-synthesizable test benches, such as an interactive SDL frontend. So you can take your HDL logic and run it directly, interactively in real time. You can play Pong by compiling the code as software.

One level lower, you can use Clash's signal-level simulator. Basically it gives you a synchronous stream of signal values, either as a lazy list (for "offline" simulation), or as an automaton that you can turn the crank on by feeding it the next clock cycle's inputs (for "online" simulation, i.e. where you want to do IO to compute the next input from the previous outputs). So at this level, you'd take your Pong circuit and use the automaton interface of the simulator to feed the virtual "pushbutton" states computed from e.g. keypresses, and then consume the output to do the rendering. Or simulate the whole circuit end-to-end and feed its output into a VGA interpreter, which you also get to write in Haskell.

If you need to debug at the Verilog level, you can use Clashilator (https://github.com/gergoerdi/clashilator) to automate FFI-ing into a Verilator-generated simulation.

However, if it is lower-level simulation you want, Clash also has you covered for that. Clashilator makes it easy to interface with the open source Verilog simulator Verilator. This is not covered in the book, but most of the coe repos come with both high- and low-level simulation harnessing included.