Retrocomputing with Clash: Haskell for FPGA Hardware Design (book)

• clash-pong

  1 7 0.0 Verilog

  Pong in Haskell / Clash, running as software using SDL and as hardware targeting FPGAs

However, all the code from the book (as collected at https://retrocla.sh/) synthesizes for real hardware FPGAs. I've been using a Nexys A7-50T (Xilinx 7-series FPGA) and old Papilio Pro (Xilinx 6-series) and Papilio One (Xilinx 3-series) FPGAs; the Nexys is my daily driver so all repos come with Shake rules for building for that. But people have also contributed support for the DECA Arrow (Intel MAX 10) and Terasic DE0-Nano (Intel Cyclone IV) to clash-pong, so you should be able to take that as a template if you want to use something else.

• clashilator

  2 19 0.0 Haskell

  Generate interface between Clash and Verilator

However, if it is lower-level simulation you want, Clash also has you covered for that. Clashilator makes it easy to interface with the open source Verilog simulator Verilator. This is not covered in the book, but most of the coe repos come with both high- and low-level simulation harnessing included.

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