bit-serial
forth-cpu
| bit-serial | forth-cpu | |
|---|---|---|
| 1 | 2 | |
| 111 | 315 | |
| - | - | |
| 6.7 | 2.6 | |
| 3 months ago | about 2 years ago | |
| VHDL | VHDL | |
| MIT License | - |
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bit-serial
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The ancient world before computers had stacks or heaps
I wrote a Forth interpreter for a SUBLEQ machine (https://github.com/howerj/subleq), and for a bit-serial machine (https://github.com/howerj/bit-serial), both of which do not have a function call stack which is a requirement of Forth. SUBLEQ also does not allow indirect loading and stores as well and requires self-modifying code to do anything non-trivial. The approach I took for both machines was to build a virtual machine that could do those things, along with cooperative multithreading. The heap, if required, is written in Forth, along with a floating point word-set (various MCUs not having instructions for floating point numbers is still fairly common, and can be implemented as calls to software functions that implement them instead).
I would imagine that other compilers took a similar approach which wasn't mentioned.
forth-cpu
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Designs targeting specific boards?
Like in my head I thought having a piece of verilog and having enough LUTs in any board would do the thing, so what meant here? An example https://github.com/howerj/forth-cpu mentions that the target board is a specific Xilinx.
- Forth SoC Written in VHDL
What are some alternatives?
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
sdram-fpga - A FPGA core for a simple SDRAM controller.
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
VHDL-Guide - VHDL Guide
pocket-cnn - CNN-to-FPGA-framework for small CNN, written in VHDL and Python
Arcade_Galaga - Galaga Arcade Core
Flo-Posit - Posit Arithmetic Cores generated with FloPoCo
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
openfpga-SNES - SNES for the Analogue Pocket