apicula
Project Apicula 🐝: bitstream documentation for Gowin FPGAs (by YosysHQ)
tomverbeure
By tomverbeure
| apicula | tomverbeure | |
|---|---|---|
| 7 | 5 | |
| 421 | - | |
| 5.0% | - | |
| 7.7 | - | |
| 23 days ago | - | |
| Verilog | ||
| MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
apicula
Posts with mentions or reviews of apicula.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-03.
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Logik: Open-source FPGA toolchain by Zero ASIC
https://github.com/YosysHQ/apicula
Project Apicula says "currently supported boards are ... [list of mostly Tang boards]" without qualification.
I wouldn't be surprised to discover that it actually is qualified support, though. Do you think the actual support is low enough that one should avoid those boards for now?
- Project Apicula adds support for DDR SERDES primitives on several GW1 devices.
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PLL Rates? Can any of the Gowin parts do 1080P?
I actually haven't, since I don't know who they are. That is a good idea though, posted https://github.com/YosysHQ/apicula/issues/169 to discuss the issue, in case someone there might be able to pick it up.
- Project Apicula: added initial PLL support for GW1N-1
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Minimal build script, and flags for yosys and nextpnr to target GW1N-LV1QN48?
You do not need any gowin software or licensing for the open source toolchain. As the other poster noted, there are a few getting started guides floating around. Alternatively, just swing by the project apicula page and work through their instructions.
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Has anyone had any experience with this ultra-cheap Chinese FPGA board - the Sipeed Tang Nano
btw.: there is also a lot of interesting progress going on in the project apicula, the open source tools for the gowin FPGAs.
tomverbeure
Posts with mentions or reviews of tomverbeure.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-04-16.
- so the timing generator seems to work ok...
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Where to get started?
Here are some of my unpublished notes on how to install the software. Maybe it’s helpful to you?
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How to debug a RISC-V soft core
I’m in the process of writing a blog post about debugging a VexRiscv soft core. It’s work in progress, but the introduction should give you an idea how things connect together in general.
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Has anyone had any experience with this ultra-cheap Chinese FPGA board - the Sipeed Tang Nano
I never finished a blog post about it, but here are the notes that I made along the way about installing the tools etc.
- Digilent JTAG HS3 - Altera
What are some alternatives?
When comparing apicula and tomverbeure you can also consider the following projects:
yosys - Yosys Open SYnthesis Suite
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
gowin_flipflop_drainer - A test case for stress testing Tang Nano 4K and 9K and Primer 20K (Gowin FPGAs)
riscv-debug-spec - Working Draft of the RISC-V Debug Specification Standard
vexriscv_ocd