tomverbeure
By tomverbeure
riscv-debug-spec
Working Draft of the RISC-V Debug Specification Standard (by riscv)
| tomverbeure | riscv-debug-spec | |
|---|---|---|
| 5 | 1 | |
| - | 435 | |
| - | 1.8% | |
| - | 9.5 | |
| - | 4 days ago | |
| Python | ||
| - | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
tomverbeure
Posts with mentions or reviews of tomverbeure.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-04-16.
- so the timing generator seems to work ok...
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Where to get started?
Here are some of my unpublished notes on how to install the software. Maybe it’s helpful to you?
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How to debug a RISC-V soft core
I’m in the process of writing a blog post about debugging a VexRiscv soft core. It’s work in progress, but the introduction should give you an idea how things connect together in general.
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Has anyone had any experience with this ultra-cheap Chinese FPGA board - the Sipeed Tang Nano
I never finished a blog post about it, but here are the notes that I made along the way about installing the tools etc.
- Digilent JTAG HS3 - Altera
riscv-debug-spec
Posts with mentions or reviews of riscv-debug-spec.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-04-16.
-
How to debug a RISC-V soft core
I want to use the RISC-V ibex core, however, I need a debugger. For that reason, I'm using the code from here, which includes a debug unit in the FPGA example compliant with the RISC-V debug specification. I managed to port the code to my FPGA but now I'm a little lost on how can I debug my applications. If I understood right, I need an Olimex adapter to connect my PC to the JTAG interface of the FPGA, but besides that, what do I need to do in order to use gdb? Sorry for my ignorance but I'm new to the field.
What are some alternatives?
When comparing tomverbeure and riscv-debug-spec you can also consider the following projects:
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
vexriscv_ocd
apicula - Project Apicula 🐝: bitstream documentation for Gowin FPGAs
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.