How to debug a RISC-V soft core

• ibex

  20 1,244 8.3 SystemVerilog

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  

I want to use the RISC-V ibex core, however, I need a debugger. For that reason, I'm using the code from here, which includes a debug unit in the FPGA example compliant with the RISC-V debug specification. I managed to port the code to my FPGA but now I'm a little lost on how can I debug my applications. If I understood right, I need an Olimex adapter to connect my PC to the JTAG interface of the FPGA, but besides that, what do I need to do in order to use gdb? Sorry for my ignorance but I'm new to the field.

• ibex

  1 2 1.8

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. (by majbthrd)

I want to use the RISC-V ibex core, however, I need a debugger. For that reason, I'm using the code from here, which includes a debug unit in the FPGA example compliant with the RISC-V debug specification. I managed to port the code to my FPGA but now I'm a little lost on how can I debug my applications. If I understood right, I need an Olimex adapter to connect my PC to the JTAG interface of the FPGA, but besides that, what do I need to do in order to use gdb? Sorry for my ignorance but I'm new to the field.

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• riscv-debug-spec

  1 429 9.5 Python

  Working Draft of the RISC-V Debug Specification Standard

  

I want to use the RISC-V ibex core, however, I need a debugger. For that reason, I'm using the code from here, which includes a debug unit in the FPGA example compliant with the RISC-V debug specification. I managed to port the code to my FPGA but now I'm a little lost on how can I debug my applications. If I understood right, I need an Olimex adapter to connect my PC to the JTAG interface of the FPGA, but besides that, what do I need to do in order to use gdb? Sorry for my ignorance but I'm new to the field.

• tomverbeure

  5 - -

I’m in the process of writing a blog post about debugging a VexRiscv soft core. It’s work in progress, but the introduction should give you an idea how things connect together in general.

• vexriscv_ocd

  3 2 6.1 Assembly

Similarly, my the README of test project might give you some pointers.

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