riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard (by riscv)

Riscv-debug-spec Alternatives

Similar projects and alternatives to riscv-debug-spec

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better riscv-debug-spec alternative or higher similarity.

riscv-debug-spec reviews and mentions

Posts with mentions or reviews of riscv-debug-spec. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-04-16.
  • How to debug a RISC-V soft core
    5 projects | /r/FPGA | 16 Apr 2021
    I want to use the RISC-V ibex core, however, I need a debugger. For that reason, I'm using the code from here, which includes a debug unit in the FPGA example compliant with the RISC-V debug specification. I managed to port the code to my FPGA but now I'm a little lost on how can I debug my applications. If I understood right, I need an Olimex adapter to connect my PC to the JTAG interface of the FPGA, but besides that, what do I need to do in order to use gdb? Sorry for my ignorance but I'm new to the field.

Stats

Basic riscv-debug-spec repo stats
1
430
9.5
5 days ago

riscv/riscv-debug-spec is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.

The primary programming language of riscv-debug-spec is Python.


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