apicula
Project Apicula 🐝: bitstream documentation for Gowin FPGAs (by YosysHQ)
yosys
Yosys Open SYnthesis Suite (by YosysHQ)
apicula | yosys | |
---|---|---|
7 | 7 | |
421 | 3,163 | |
2.9% | 1.8% | |
7.7 | 9.9 | |
23 days ago | 6 days ago | |
Verilog | C++ | |
MIT License | ISC License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
apicula
Posts with mentions or reviews of apicula.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-03.
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Logik: Open-source FPGA toolchain by Zero ASIC
https://github.com/YosysHQ/apicula
Project Apicula says "currently supported boards are ... [list of mostly Tang boards]" without qualification.
I wouldn't be surprised to discover that it actually is qualified support, though. Do you think the actual support is low enough that one should avoid those boards for now?
- Project Apicula adds support for DDR SERDES primitives on several GW1 devices.
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PLL Rates? Can any of the Gowin parts do 1080P?
I actually haven't, since I don't know who they are. That is a good idea though, posted https://github.com/YosysHQ/apicula/issues/169 to discuss the issue, in case someone there might be able to pick it up.
- Project Apicula: added initial PLL support for GW1N-1
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Minimal build script, and flags for yosys and nextpnr to target GW1N-LV1QN48?
You do not need any gowin software or licensing for the open source toolchain. As the other poster noted, there are a few getting started guides floating around. Alternatively, just swing by the project apicula page and work through their instructions.
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Has anyone had any experience with this ultra-cheap Chinese FPGA board - the Sipeed Tang Nano
btw.: there is also a lot of interesting progress going on in the project apicula, the open source tools for the gowin FPGAs.
yosys
Posts with mentions or reviews of yosys.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-20.
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Efinix makes software free to access - no longer do you need a dev board
I see efinix in the yosys tree, https://github.com/YosysHQ/yosys/blob/master/techlibs/efinix/synth_efinix.cc
- Minimal build script, and flags for yosys and nextpnr to target GW1N-LV1QN48?
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Where in the process is circuit minimization done?
Here is just a small list of passes, with their source code: https://github.com/YosysHQ/yosys/tree/master/passes/opt.
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Do you work in a mixed HDL shop?
To be honest, I have no clue, I've never used GHDL. For Yosys I'm not too sure either but their README indicates that it has mostly complete Verilog-2005 support, and a few features from SystemVerilog too.
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3rd party toolchain for Spartan3?
Yosys has preliminary support for Spartan 3 devices.
- "Formal Verification Specialist Oski Joins NVIDIA"
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Glitches In Clock Gating Cell
See the simulation waveform of the Post-Control CG circuit and its corresponding gate-level circuit
What are some alternatives?
When comparing apicula and yosys you can also consider the following projects:
tomverbeure
abc - ABC: System for Sequential Logic Synthesis and Formal Verification
gowin_flipflop_drainer - A test case for stress testing Tang Nano 4K and 9K and Primer 20K (Gowin FPGAs)
oss-cad-suite-build - Multi-platform nightly builds of open source digital design and verification tools