apicula VS gowin_flipflop_drainer

https://github.com/YosysHQ/apicula

Project Apicula says "currently supported boards are ... [list of mostly Tang boards]" without qualification.

I wouldn't be surprised to discover that it actually is qualified support, though. Do you think the actual support is low enough that one should avoid those boards for now?

I actually haven't, since I don't know who they are. That is a good idea though, posted https://github.com/YosysHQ/apicula/issues/169 to discuss the issue, in case someone there might be able to pick it up.

You do not need any gowin software or licensing for the open source toolchain. As the other poster noted, there are a few getting started guides floating around. Alternatively, just swing by the project apicula page and work through their instructions.

btw.: there is also a lot of interesting progress going on in the project apicula, the open source tools for the gowin FPGAs.

You can find a repro of this effect at https://github.com/juj/gowin_flipflop_drainer/ that you can play with yourself. See also https://www.reddit.com/r/FPGA/comments/101pagf/sipeed_tang_nano_4k_9k_gowin_fpgas_become/

Right now the latest struggle is that we are blocked on this issue: https://github.com/juj/gowin_flipflop_drainer which I am not sure if it will turn out to be a killer for our project or not. Hoping for the best.

Overall I have enjoyed developing on these boards, although I should state that there is a bit of an outstanding trouble with these boards that has blocked my design from proceeding (check out https://github.com/juj/gowin_flipflop_drainer for details). It is still unclear if that only affects video application, general SERDES applications, or what.

If someone has a Twitter account, could you ask Sipeed whether the new Tang Nano 20K will be immune to this problem https://github.com/juj/gowin_flipflop_drainer ?

If this was a power issue, given that the "nonsense adders" in the test case in https://github.com/juj/gowin_flipflop_drainer are operating at a high clock speed that is desynchronized from the video subsystem, then I would expect that there would have been noise present in the power delivery more or less "constantly", and at random times with respect to the video signals.

You can find the test case repository at https://github.com/juj/gowin_flipflop_drainer

I concur with Sipeed. I really like them as well, they are lean and easy to get started, although right now I am struggling with a hardware instability problem on those boards :/ ( https://github.com/juj/gowin_flipflop_drainer )