Sipeed Tang Nano 4K, 9K (Gowin FPGAs) become unstable when lots of flip flops are in use

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  • gowin_flipflop_drainer

    A test case for stress testing Tang Nano 4K and 9K and Primer 20K (Gowin FPGAs)

    • If this was a power issue, given that the "nonsense adders" in the test case in https://github.com/juj/gowin_flipflop_drainer are operating at a high clock speed that is desynchronized from the video subsystem, then I would expect that there would have been noise present in the power delivery more or less "constantly", and at random times with respect to the video signals.

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