apicula
Project Apicula 🐝: bitstream documentation for Gowin FPGAs (by YosysHQ)
gowin_flipflop_drainer
A test case for stress testing Tang Nano 4K and 9K and Primer 20K (Gowin FPGAs) (by juj)
apicula | gowin_flipflop_drainer | |
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7 | 8 | |
421 | 21 | |
5.0% | - | |
7.7 | 1.1 | |
23 days ago | about 1 year ago | |
Verilog | Verilog | |
MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
apicula
Posts with mentions or reviews of apicula.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-03.
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Logik: Open-source FPGA toolchain by Zero ASIC
https://github.com/YosysHQ/apicula
Project Apicula says "currently supported boards are ... [list of mostly Tang boards]" without qualification.
I wouldn't be surprised to discover that it actually is qualified support, though. Do you think the actual support is low enough that one should avoid those boards for now?
- Project Apicula adds support for DDR SERDES primitives on several GW1 devices.
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PLL Rates? Can any of the Gowin parts do 1080P?
I actually haven't, since I don't know who they are. That is a good idea though, posted https://github.com/YosysHQ/apicula/issues/169 to discuss the issue, in case someone there might be able to pick it up.
- Project Apicula: added initial PLL support for GW1N-1
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Minimal build script, and flags for yosys and nextpnr to target GW1N-LV1QN48?
You do not need any gowin software or licensing for the open source toolchain. As the other poster noted, there are a few getting started guides floating around. Alternatively, just swing by the project apicula page and work through their instructions.
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Has anyone had any experience with this ultra-cheap Chinese FPGA board - the Sipeed Tang Nano
btw.: there is also a lot of interesting progress going on in the project apicula, the open source tools for the gowin FPGAs.
gowin_flipflop_drainer
Posts with mentions or reviews of gowin_flipflop_drainer.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-02-19.
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PLL Rates? Can any of the Gowin parts do 1080P?
You can find a repro of this effect at https://github.com/juj/gowin_flipflop_drainer/ that you can play with yourself. See also https://www.reddit.com/r/FPGA/comments/101pagf/sipeed_tang_nano_4k_9k_gowin_fpgas_become/
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GOWIN vs EFINIX
Right now the latest struggle is that we are blocked on this issue: https://github.com/juj/gowin_flipflop_drainer which I am not sure if it will turn out to be a killer for our project or not. Hoping for the best.
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GOWIN FGA questions
Overall I have enjoyed developing on these boards, although I should state that there is a bit of an outstanding trouble with these boards that has blocked my design from proceeding (check out https://github.com/juj/gowin_flipflop_drainer for details). It is still unclear if that only affects video application, general SERDES applications, or what.
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Tang Nano 20K announced
If someone has a Twitter account, could you ask Sipeed whether the new Tang Nano 20K will be immune to this problem https://github.com/juj/gowin_flipflop_drainer ?
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Sipeed Tang Nano 4K, 9K (Gowin FPGAs) become unstable when lots of flip flops are in use
If this was a power issue, given that the "nonsense adders" in the test case in https://github.com/juj/gowin_flipflop_drainer are operating at a high clock speed that is desynchronized from the video subsystem, then I would expect that there would have been noise present in the power delivery more or less "constantly", and at random times with respect to the video signals.
You can find the test case repository at https://github.com/juj/gowin_flipflop_drainer
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Low prices FPGA dev board.
I concur with Sipeed. I really like them as well, they are lean and easy to get started, although right now I am struggling with a hardware instability problem on those boards :/ ( https://github.com/juj/gowin_flipflop_drainer )
What are some alternatives?
When comparing apicula and gowin_flipflop_drainer you can also consider the following projects:
tomverbeure
tang4Kramblings
yosys - Yosys Open SYnthesis Suite
TangNano-9K-example - TangNano-9K-example project